From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751670AbeFBNsz (ORCPT ); Sat, 2 Jun 2018 09:48:55 -0400 Received: from mail-ot0-f193.google.com ([74.125.82.193]:37424 "EHLO mail-ot0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751503AbeFBNsx (ORCPT ); Sat, 2 Jun 2018 09:48:53 -0400 X-Google-Smtp-Source: ADUXVKLRI18RT4TLCEL3CPu03OPeQ+tHuI516pxYE4gmOBh7T2zdJOD7F3gOQNL3S//zekbmGLJVYPDjDmsIU4tO+fY= MIME-Version: 1.0 In-Reply-To: <1439344955.9677.1526991935718@email.1und1.de> References: <1526959560-6014-1-git-send-email-Anson.Huang@nxp.com> <1439344955.9677.1526991935718@email.1und1.de> From: Fabio Estevam Date: Sat, 2 Jun 2018 10:48:52 -0300 Message-ID: Subject: Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates To: Stefan Wahren Cc: Michael Trimarchi , Rob Herring , Fabio Estevam , Mark Rutland , Anson Huang , Matteo Lisi , Shawn Guo , Sascha Hauer , Michael Turquette , Stephen Boyd , linux-clk , NXP Linux Team , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-kernel , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Stefan, On Tue, May 22, 2018 at 9:25 AM, Stefan Wahren wrote: >> --- a/include/dt-bindings/clock/imx6ul-clock.h >> +++ b/include/dt-bindings/clock/imx6ul-clock.h >> @@ -242,20 +242,25 @@ >> #define IMX6UL_CLK_CKO2_PODF 229 >> #define IMX6UL_CLK_CKO2 230 >> #define IMX6UL_CLK_CKO 231 >> +#define IMX6UL_CLK_GPIO1 232 >> +#define IMX6UL_CLK_GPIO2 233 >> +#define IMX6UL_CLK_GPIO3 234 >> +#define IMX6UL_CLK_GPIO4 235 >> +#define IMX6UL_CLK_GPIO5 236 > > this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel. Good point! I will send a fix for f5a4670de96678 ("clk: imx: Add new clo01 and clo2 controlled by CCOSR") which did the same reordering. Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: festevam@gmail.com (Fabio Estevam) Date: Sat, 2 Jun 2018 10:48:52 -0300 Subject: [PATCH 1/2] clk: imx6ul: add GPIO clock gates In-Reply-To: <1439344955.9677.1526991935718@email.1und1.de> References: <1526959560-6014-1-git-send-email-Anson.Huang@nxp.com> <1439344955.9677.1526991935718@email.1und1.de> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Stefan, On Tue, May 22, 2018 at 9:25 AM, Stefan Wahren wrote: >> --- a/include/dt-bindings/clock/imx6ul-clock.h >> +++ b/include/dt-bindings/clock/imx6ul-clock.h >> @@ -242,20 +242,25 @@ >> #define IMX6UL_CLK_CKO2_PODF 229 >> #define IMX6UL_CLK_CKO2 230 >> #define IMX6UL_CLK_CKO 231 >> +#define IMX6UL_CLK_GPIO1 232 >> +#define IMX6UL_CLK_GPIO2 233 >> +#define IMX6UL_CLK_GPIO3 234 >> +#define IMX6UL_CLK_GPIO4 235 >> +#define IMX6UL_CLK_GPIO5 236 > > this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel. Good point! I will send a fix for f5a4670de96678 ("clk: imx: Add new clo01 and clo2 controlled by CCOSR") which did the same reordering. Thanks