From mboxrd@z Thu Jan  1 00:00:00 1970
From: Fabio Estevam <festevam@gmail.com>
Date: Mon, 29 May 2017 08:17:34 -0300
Subject: [U-Boot] [PATCH 1/4] mmc: fsl_esdhc: Allow all supported
 prescaler values
In-Reply-To: <1493805546-3567-1-git-send-email-benoit@wsystem.com>
References: <1493805546-3567-1-git-send-email-benoit@wsystem.com>
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On Wed, May 3, 2017 at 6:59 AM, Benoît Thébaudeau <benoit@wsystem.com> wrote:
> On i.MX, SYSCTL.SDCLKFS may be set to 0 in order to make the SD clock
> frequency prescaler divide by 1 in SDR mode. In DDR mode, the prescaler
> can divide by up to 512. Allow both of these settings.
>
> The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25,
> this change makes it possible to get 48 MHz from the USB PLL
> (240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL
> (240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
>
> Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>