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From: festevam@gmail.com (Fabio Estevam)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 2/2] ARM: imx6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority
Date: Thu, 20 Feb 2014 10:34:26 -0300	[thread overview]
Message-ID: <CAOMZO5C0kcre6=JW=vXSaYL_zydvnwZYCV92Rg1_b=feAGr9qw@mail.gmail.com> (raw)
In-Reply-To: <1392896673-13627-2-git-send-email-p.zabel@pengutronix.de>

On Thu, Feb 20, 2014 at 8:44 AM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> This is needed so that the IPU framebuffer scanout cannot be
> starved by VPU or GPU activity.
> Some boards like the SabreLite and SabreSD seem to set this in
> the DCD already, but the documented register reset values do not
> contain the necessary settings.
>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

Yes, better to configure it in the kernel than relying on the
bootloader to do this setup.

Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>

  reply	other threads:[~2014-02-20 13:34 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-02-20 11:44 [RFC PATCH 1/2] ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr Philipp Zabel
2014-02-20 11:44 ` [RFC PATCH 2/2] ARM: imx6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority Philipp Zabel
2014-02-20 13:34   ` Fabio Estevam [this message]
2014-02-21  2:19   ` Shawn Guo
2014-02-21 10:28     ` Philipp Zabel
2014-02-24  2:03       ` Shawn Guo
2014-02-24  9:32         ` Philipp Zabel

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