From mboxrd@z Thu Jan  1 00:00:00 1970
From: Fabio Estevam <festevam@gmail.com>
Date: Wed, 3 Aug 2016 10:51:59 -0300
Subject: [U-Boot] [PATCH] mtd: nand: mxs: fix cache alignment for cache
 lines >32
In-Reply-To: <20160802065518.24140-1-stefan@agner.ch>
References: <20160802065518.24140-1-stefan@agner.ch>
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On Tue, Aug 2, 2016 at 3:55 AM, Stefan Agner <stefan@agner.ch> wrote:
> From: Stefan Agner <stefan.agner@toradex.com>
>
> Currently the command buffer gets allocated with a size of 32 bytes.
> This causes warning messages on systems with cache lines bigger than
> 32 bytes:
> CACHE: Misaligned operation at range [9df17a00, 9df17a20]
>
> Define command buffer to be at least 32 bytes, but more if cache
> line is bigger.
>
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> ---
> This appeared after Simon enable the message in check_cache_range
> by default...

On mx6ul pico I also get similar warnings even though NAND is not used
on this board:

U-Boot 2016.09-rc1-00245-gad6a303 (Aug 03 2016 - 10:31:52 -0300)

CPU:   Freescale i.MX6UL rev1.0 at 396 MHz
Reset cause: WDOG
Board: PICO-IMX6UL-EMMC
I2C:   ready
DRAM:  256 MiB
CACHE: Misaligned operation at range [8fff0000, 8fff0004]
CACHE: Misaligned operation at range [8fff0024, 8fff0028]
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   FEC
Hit any key to stop autoboot:  0

Looks like we need a more generic fix?

Thanks