From: Fabio Estevam <festevam@gmail.com>
To: Francesco Dolcini <francesco.dolcini@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>, Marek Vasut <marex@denx.de>,
Marcel Ziswiler <marcel.ziswiler@toradex.com>,
"NXP i.MX U-Boot Team" <uboot-imx@nxp.com>,
Tim Harvey <tharvey@gateworks.com>,
U-Boot-Denx <u-boot@lists.denx.de>
Subject: Re: [PATCH v1 2/2] board: apalis_imx6: DDR init using mx6_dram_cfg()
Date: Fri, 24 Jun 2022 13:47:03 -0300 [thread overview]
Message-ID: <CAOMZO5CEd-VwhAmjeck0wjvUvteF1t-j5ihi7nU9ecemj5ExTg@mail.gmail.com> (raw)
In-Reply-To: <20220624103336.536999-3-francesco.dolcini@toradex.com>
On Fri, Jun 24, 2022 at 7:33 AM Francesco Dolcini
<francesco.dolcini@toradex.com> wrote:
>
> Do DDR initialization using the procedural mx6_dram_cfg() instead of
> programming the MMDC using a raw list of register/value pairs, this
> solves some rare boot failures on specific "bad" modules.
>
> Calibration values, DDR geometry are unchanged, memory timings are
> updated according to the relevant memory datasheet, no changes on
> the power consumption.
>
> For IT temperature range SKUs CL is decreased from 8 to 7 and tFAW
> value is increased, for commercial temperature range SKUs some
> changes on ODT parameters.
>
> This change was validated over a range of different apalis-imx6 SoM, on
> the whole working temperature range with weeks of continuous testing.
>
> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
next prev parent reply other threads:[~2022-06-24 16:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-24 10:33 [PATCH v1 0/2] Fix Apalis iMX6 Memory Init Francesco Dolcini
2022-06-24 10:33 ` [PATCH v1 1/2] mx6: ddr: Fix disabling on-die termination Francesco Dolcini
2022-06-24 16:46 ` Fabio Estevam
2022-06-27 7:02 ` Marcel Ziswiler
2022-06-24 10:33 ` [PATCH v1 2/2] board: apalis_imx6: DDR init using mx6_dram_cfg() Francesco Dolcini
2022-06-24 16:47 ` Fabio Estevam [this message]
2022-06-27 7:03 ` Marcel Ziswiler
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