From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C85C7C433F5 for ; Fri, 6 May 2022 14:44:28 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id ADFBD80584; Fri, 6 May 2022 16:44:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="ND2ZqZBH"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id B055B8006F; Fri, 6 May 2022 16:44:24 +0200 (CEST) Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4062E839E6 for ; Fri, 6 May 2022 16:44:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=michael@amarulasolutions.com Received: by mail-pl1-x62d.google.com with SMTP id d22so7621512plr.9 for ; Fri, 06 May 2022 07:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=s7zUQbnNJqu/B67WESxXE77Zl2asZxDuJkDjhPUoViI=; b=ND2ZqZBHgn4YEKrY16Lgr7qsh44LuFe0G88jKDTlNmnA48S3c3t/W9lGkiEbSyy1M7 +qXT8bY8eULrvrRkCoTMxJKavKK51cb08WtzYIdGStkIcYmRhLiyqLGhdnFGf3Yn1Rj3 yS2RJHY54qssp9fxGpp8+zkMleTYLW/cf1VmI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=s7zUQbnNJqu/B67WESxXE77Zl2asZxDuJkDjhPUoViI=; b=uVA53oJQ5uC3ufEXMd2bdwIBSnmRHWuLPBeHqM8b/uiXBS3GCitq6nIhDjpOIb6PVp 4/LgyZge8YVYc1vcP0Tz7sAsuVX495OVfGtYXElIPUApgzCv0HVo7L8Ujfz9X7d/7zyY EBuZrVhMDrozbgUBUC665jKS47UKoma3JwnxUSFGvecrwOthq/ASR8nn6rTDRV9iHnwF 48/VZ/qsHek15hWvp5w9b1S/WCeyf5WLAfaSZsoDVMvzv0L4oM+6oXxP+iZDCDNWLkLD 1wcq6J/cFfyWrOVT4mwuQQMdSkefrWOilcogsyc3Z8LuhnkUjK+MgYyIaS6dQVwQMhxq hUbQ== X-Gm-Message-State: AOAM530UuodaNemSYxebovUrKGJ3SUM29TrFMNMzm6R5xWqZ3CTvtKX3 wgeQeMHuIGUvTmlO54cFconpBE2yGKvAl8VW/H/5kw== X-Google-Smtp-Source: ABdhPJz0dS30QEytKQJrvNuxb5e1Nhz2Ia7MffjLl4fQMo375wMhGea4JioZwdh4Khgqgzj4BvFoxjpp3aLQZG4ykWg= X-Received: by 2002:a17:902:7293:b0:15e:a7b6:4dd1 with SMTP id d19-20020a170902729300b0015ea7b64dd1mr4063264pll.97.1651848255422; Fri, 06 May 2022 07:44:15 -0700 (PDT) MIME-Version: 1.0 References: <20220427055025.231586-1-michael@amarulasolutions.com> <20220427055025.231586-3-michael@amarulasolutions.com> <20220506144110.d4sthydoa7e5yzv5@umbrella> In-Reply-To: <20220506144110.d4sthydoa7e5yzv5@umbrella> From: Michael Nazzareno Trimarchi Date: Fri, 6 May 2022 16:44:03 +0200 Message-ID: Subject: Re: [PATCH V2 2/4] mtd: nand: mxs_nand_spl: Fix bad block skipping To: Han Xu Cc: U-Boot-Denx , Ye Li , Stefano Babic , Miquel Raynal , Fabio Estevam , Dario Binacchi , Sean Anderson , linux-kernel@amarulasolutions.com, Jagan Teki , "Ariel D'Alessandro" , Fabio Estevam Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hi Thank you. What is the reply from bootrom team? Michael On Fri, May 6, 2022 at 4:41 PM Han Xu wrote: > > On 22/04/27 07:50AM, Michael Trimarchi wrote: > > The specific implementation was having bug. Those bugs are since > > the beginning of the implementation. Some manufactures can receive > > this bug in their SPL code. This bug start to be more visible on > > architecture that has complicated boot process like imx8mn. Older > > version of uboot has the same problem only if the bad block > > appear in correspoding of befine of u-boot image. In order to > > adjust the function we scan from the first block. The logic > > is not changed to have a simple way to fix without get regression. > > > > The problematic part of old code was in this part: > > > > while (is_badblock(mtd, offs, 1)) { > > page = page + nand_page_per_block; > > /* Check i we've reached the end of flash. */ > > if (page >= mtd->size >> chip->page_shift) { > > free(page_buf); > > return -ENOMEM; > > } > > } > > > > Even we fix it adding increment of the offset of one erase block size > > we don't fix the problem, because the first erase block where the > > image start is not checked. The code was tested on an imx8mn where > > the boot rom api was not able to skip it. Apart of that other > > architecure are using this code and all boards that has nand as boot > > device can be affected > > > > Cc: Han Xu > > Cc: Fabio Estevam > > Signed-off-by: Michael Trimarchi > > Acked-by: Han Xu > > > --- > > V1->V2: > > - Adjust the commit message > > - Add Cc Han Xu and Fabio > > - fix size >= 0 to > 0 > > --- > > drivers/mtd/nand/raw/mxs_nand_spl.c | 90 ++++++++++++++++------------- > > 1 file changed, 49 insertions(+), 41 deletions(-) > > > > diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c > > index 59a67ee414..2bfb181007 100644 > > --- a/drivers/mtd/nand/raw/mxs_nand_spl.c > > +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c > > @@ -218,14 +218,14 @@ void nand_init(void) > > mxs_nand_setup_ecc(mtd); > > } > > > > -int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) > > +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) > > { > > - struct nand_chip *chip; > > - unsigned int page; > > + unsigned int sz; > > + unsigned int block, lastblock; > > + unsigned int page, page_offset; > > unsigned int nand_page_per_block; > > - unsigned int sz = 0; > > + struct nand_chip *chip; > > u8 *page_buf = NULL; > > - u32 page_off; > > > > chip = mtd_to_nand(mtd); > > if (!chip->numchips) > > @@ -235,47 +235,42 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf) > > if (!page_buf) > > return -ENOMEM; > > > > - page = offs >> chip->page_shift; > > - page_off = offs & (mtd->writesize - 1); > > + /* offs has to be aligned to a page address! */ > > + block = offs / mtd->erasesize; > > + lastblock = (offs + size - 1) / mtd->erasesize; > > + page = (offs % mtd->erasesize) / mtd->writesize; > > + page_offset = offs % mtd->writesize; > > nand_page_per_block = mtd->erasesize / mtd->writesize; > > > > - debug("%s offset:0x%08x len:%d page:%x\n", __func__, offs, size, page); > > - > > - while (size) { > > - if (mxs_read_page_ecc(mtd, page_buf, page) < 0) > > - return -1; > > - > > - if (size > (mtd->writesize - page_off)) > > - sz = (mtd->writesize - page_off); > > - else > > - sz = size; > > - > > - memcpy(buf, page_buf + page_off, sz); > > - > > - offs += mtd->writesize; > > - page++; > > - buf += (mtd->writesize - page_off); > > - page_off = 0; > > - size -= sz; > > - > > - /* > > - * Check if we have crossed a block boundary, and if so > > - * check for bad block. > > - */ > > - if (!(page % nand_page_per_block)) { > > - /* > > - * Yes, new block. See if this block is good. If not, > > - * loop until we find a good block. > > - */ > > - while (is_badblock(mtd, offs, 1)) { > > - page = page + nand_page_per_block; > > - /* Check i we've reached the end of flash. */ > > - if (page >= mtd->size >> chip->page_shift) { > > + while (block <= lastblock && size > 0) { > > + if (!is_badblock(mtd, mtd->erasesize * block, 1)) { > > + /* Skip bad blocks */ > > + while (page < nand_page_per_block) { > > + int curr_page = nand_page_per_block * block + page; > > + > > + if (mxs_read_page_ecc(mtd, page_buf, curr_page) < 0) { > > free(page_buf); > > - return -ENOMEM; > > + return -EIO; > > } > > + > > + if (size > (mtd->writesize - page_offset)) > > + sz = (mtd->writesize - page_offset); > > + else > > + sz = size; > > + > > + memcpy(dst, page_buf + page_offset, sz); > > + dst += sz; > > + size -= sz; > > + page_offset = 0; > > + page++; > > } > > + > > + page = 0; > > + } else { > > + lastblock++; > > } > > + > > + block++; > > } > > > > free(page_buf); > > @@ -294,6 +289,19 @@ void nand_deselect(void) > > > > u32 nand_spl_adjust_offset(u32 sector, u32 offs) > > { > > - /* Handle the offset adjust in nand_spl_load_image,*/ > > + unsigned int block, lastblock; > > + > > + block = sector / mtd->erasesize; > > + lastblock = (sector + offs) / mtd->erasesize; > > + > > + while (block <= lastblock) { > > + if (is_badblock(mtd, block * mtd->erasesize, 1)) { > > + offs += mtd->erasesize; > > + lastblock++; > > + } > > + > > + block++; > > + } > > + > > return offs; > > } > > -- > > 2.25.1 > > -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com