From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7DD80C433EF for ; Wed, 16 Mar 2022 19:07:27 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id AE7A183A3A; Wed, 16 Mar 2022 20:07:24 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="n07WGNaT"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A5D9683955; Wed, 16 Mar 2022 20:07:22 +0100 (CET) Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 62B3F83ADA for ; Wed, 16 Mar 2022 20:07:15 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=michael@amarulasolutions.com Received: by mail-pf1-x42b.google.com with SMTP id s8so4797480pfk.12 for ; Wed, 16 Mar 2022 12:07:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=CCdP8AlsiixJE/S/8Lccw5PfVOUd/JUooxzqhMSflfo=; b=n07WGNaT4pT8kcrMPQ/VWte9Nmyopx0Cq4dO/Rx+aJdvGBxHGAMBzGa4RnnxL2AhD/ tH3WnZES3lwQWkAd5j8afgqNSijLudn2AUP9TQjCx5rChOgP+jBwrp/DQmAdmGaRcudp YZP1VR30oPTh0gSFlF2TzTyUefw0VrVgd4fkg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CCdP8AlsiixJE/S/8Lccw5PfVOUd/JUooxzqhMSflfo=; b=PqzZ0WmFtQu6+LB63FFpstDsEQPGiXwHcmvOVvXhz3dpMgUAuxO5S5UhhqExjOeEPg +tKDJrQ2S9p647LfPdc8qllFW81r9+kCBwVPd79PB9NX6uZmtxSkdTp9FDgWaq/vsRo0 mgkrdSccLV0gJMekWdfRvN64xF4h8ACxJUsX8ca80GV04d/eCfjXxIVvJa7mHX1WSXV0 r/KWhZwB8kqR9z4ndmfjt8J3+HvRmyn/j+sG3qTHV68TuBTFMRzlKAwNUvcyZ0NVBC4j 9DWCeikiHaheW4iwnuDLCT8w/oIhsggXFb2DWlR9OAU1XREsaezgMneVzsw422ZAKIHI XwiQ== X-Gm-Message-State: AOAM530hh/2hp9rbsWT1xA2HVYELXces2NFXYDrq5rws5jGOTlEsutQ4 o+upL05R92j5eYmHgTTS35I023LKCreraOf6kE5IcQ== X-Google-Smtp-Source: ABdhPJxPPR5sjvCwr1qQB/N8gNB4FmYvToeSxV4Wkiyl8IN43kepDRCmfUKnuyS9v728Tb1sq4+HPpRp9V2L+CwVPVc= X-Received: by 2002:aa7:8ec2:0:b0:4f7:4a9:7fcd with SMTP id b2-20020aa78ec2000000b004f704a97fcdmr1346078pfr.26.1647457633408; Wed, 16 Mar 2022 12:07:13 -0700 (PDT) MIME-Version: 1.0 References: <20220316152746.47768-1-tommaso.merciai@amarulasolutions.com> <20220316152746.47768-5-tommaso.merciai@amarulasolutions.com> In-Reply-To: <20220316152746.47768-5-tommaso.merciai@amarulasolutions.com> From: Michael Nazzareno Trimarchi Date: Wed, 16 Mar 2022 20:07:01 +0100 Message-ID: Subject: Re: [PATCH v2 4/9] arm: imx: imx8mm: add enable_pwm_clk function To: Tommaso Merciai Cc: Stefano Babic , Fabio Estevam , "NXP i.MX U-Boot Team" , Peng Fan , Ye Li , Alice Guo , Andrey Zhizhikin , Marek Vasut , =?UTF-8?B?TWFyZWsgQmVow7pu?= , u-boot@lists.denx.de Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hi Tommaaso On Wed, Mar 16, 2022 at 4:28 PM Tommaso Merciai wrote: > > Add function enable_pwm_clk into in clock_imx8mm.c. This > function first configure, then enable pwm clock from clock control > register. The following configuration is used: > > source(0) -> 24 MHz ref clock > div(0) -> no division for this clock > > References: > - iMX8MMRM.pdf p 303 > > Signed-off-by: Tommaso Merciai > --- > Changes since v1: > - Fix enable_pwm_clk function implementation. Now is generic for all pwm clks > > arch/arm/mach-imx/imx8m/clock_imx8mm.c | 53 ++++++++++++++++++++++++++ > 1 file changed, 53 insertions(+) > > diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c > index 49945faf2c..ffb9456607 100644 > --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c > +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c > @@ -313,6 +313,59 @@ void enable_usboh3_clk(unsigned int enable) > } > } > > +void enable_pwm_clk(u32 index, unsigned char enable) > +{ > + switch (index) { > + case 0: > + if (enable) { > + clock_enable(CCGR_PWM1, false); > + clock_set_target_val(PWM1_CLK_ROOT, CLK_ROOT_ON | > + CLK_ROOT_SOURCE_SEL(0) | > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1)); > + clock_enable(CCGR_PWM1, true); > + } else { > + clock_enable(CCGR_PWM1, false); Pwm is alway before set to false and then enable. Make sense to move out. Then all the code is look quite the same apart minior change Can you clean up in order to have a more compact implementation? Michael > + } > + return; > + case 1: > + if (enable) { > + clock_enable(CCGR_PWM2, false); > + clock_set_target_val(PWM2_CLK_ROOT, CLK_ROOT_ON | > + CLK_ROOT_SOURCE_SEL(0) | > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1)); > + clock_enable(CCGR_PWM2, true); > + } else { > + clock_enable(CCGR_PWM2, false); > + } > + return; > + case 2: > + if (enable) { > + clock_enable(CCGR_PWM3, false); > + clock_set_target_val(PWM3_CLK_ROOT, CLK_ROOT_ON | > + CLK_ROOT_SOURCE_SEL(0) | > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1)); > + clock_enable(CCGR_PWM3, true); > + } else { > + clock_enable(CCGR_PWM3, false); > + } > + return; > + case 3: > + if (enable) { > + clock_enable(CCGR_PWM4, false); > + clock_set_target_val(PWM4_CLK_ROOT, CLK_ROOT_ON | > + CLK_ROOT_SOURCE_SEL(0) | > + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1)); > + clock_enable(CCGR_PWM4, true); > + } else { > + clock_enable(CCGR_PWM4, false); > + } > + return; > + default: > + printf("Invalid pwm index\n"); > + return; > + } > +} > + Please factorize things that are always eegual > void init_uart_clk(u32 index) > { > /* > -- > 2.25.1 > -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael@amarulasolutions.com __________________________________ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info@amarulasolutions.com www.amarulasolutions.com