From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751305AbeFBOER (ORCPT ); Sat, 2 Jun 2018 10:04:17 -0400 Received: from mail-wr0-f193.google.com ([209.85.128.193]:33533 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750740AbeFBOEP (ORCPT ); Sat, 2 Jun 2018 10:04:15 -0400 X-Google-Smtp-Source: ADUXVKIFNVtzFgIuHR66ymzFNJsLRGu+LGH6+zBgezxsBYETQpyIdkBuTEJFVWOs1Ls4L/991iJ0FAPjahVNCfKSULA= MIME-Version: 1.0 In-Reply-To: References: <1526959560-6014-1-git-send-email-Anson.Huang@nxp.com> <1439344955.9677.1526991935718@email.1und1.de> From: Michael Nazzareno Trimarchi Date: Sat, 2 Jun 2018 16:04:13 +0200 Message-ID: Subject: Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates To: Fabio Estevam Cc: Stefan Wahren , Rob Herring , Fabio Estevam , Mark Rutland , Anson Huang , Matteo Lisi , Shawn Guo , Sascha Hauer , Michael Turquette , Stephen Boyd , linux-clk , NXP Linux Team , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-kernel , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi On Sat, Jun 2, 2018 at 3:48 PM, Fabio Estevam wrote: > Hi Stefan, > > On Tue, May 22, 2018 at 9:25 AM, Stefan Wahren wrote: > >>> --- a/include/dt-bindings/clock/imx6ul-clock.h >>> +++ b/include/dt-bindings/clock/imx6ul-clock.h >>> @@ -242,20 +242,25 @@ >>> #define IMX6UL_CLK_CKO2_PODF 229 >>> #define IMX6UL_CLK_CKO2 230 >>> #define IMX6UL_CLK_CKO 231 >>> +#define IMX6UL_CLK_GPIO1 232 >>> +#define IMX6UL_CLK_GPIO2 233 >>> +#define IMX6UL_CLK_GPIO3 234 >>> +#define IMX6UL_CLK_GPIO4 235 >>> +#define IMX6UL_CLK_GPIO5 236 >> >> this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel. > > Good point! I will send a fix for f5a4670de96678 ("clk: imx: Add new > clo01 and clo2 controlled > by CCOSR") which did the same reordering. > ull is a preatty new platform so one board was listed. Are you sure that we need? Michael > Thanks -- | Michael Nazzareno Trimarchi Amarula Solutions BV | | COO - Founder Cruquiuskade 47 | | +31(0)851119172 Amsterdam 1018 AM NL | | [`as] http://www.amarulasolutions.com | From mboxrd@z Thu Jan 1 00:00:00 1970 From: michael@amarulasolutions.com (Michael Nazzareno Trimarchi) Date: Sat, 2 Jun 2018 16:04:13 +0200 Subject: [PATCH 1/2] clk: imx6ul: add GPIO clock gates In-Reply-To: References: <1526959560-6014-1-git-send-email-Anson.Huang@nxp.com> <1439344955.9677.1526991935718@email.1und1.de> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi On Sat, Jun 2, 2018 at 3:48 PM, Fabio Estevam wrote: > Hi Stefan, > > On Tue, May 22, 2018 at 9:25 AM, Stefan Wahren wrote: > >>> --- a/include/dt-bindings/clock/imx6ul-clock.h >>> +++ b/include/dt-bindings/clock/imx6ul-clock.h >>> @@ -242,20 +242,25 @@ >>> #define IMX6UL_CLK_CKO2_PODF 229 >>> #define IMX6UL_CLK_CKO2 230 >>> #define IMX6UL_CLK_CKO 231 >>> +#define IMX6UL_CLK_GPIO1 232 >>> +#define IMX6UL_CLK_GPIO2 233 >>> +#define IMX6UL_CLK_GPIO3 234 >>> +#define IMX6UL_CLK_GPIO4 235 >>> +#define IMX6UL_CLK_GPIO5 236 >> >> this change looks like a breakage of devicetree ABI. You are changing the mean of the existing clock IDs on i.MX6ULL, which probably regress the combination of older DTBs with newer kernel. > > Good point! I will send a fix for f5a4670de96678 ("clk: imx: Add new > clo01 and clo2 controlled > by CCOSR") which did the same reordering. > ull is a preatty new platform so one board was listed. Are you sure that we need? Michael > Thanks -- | Michael Nazzareno Trimarchi Amarula Solutions BV | | COO - Founder Cruquiuskade 47 | | +31(0)851119172 Amsterdam 1018 AM NL | | [`as] http://www.amarulasolutions.com |