From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35735) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzByU-0005vD-Jd for qemu-devel@nongnu.org; Mon, 23 Jun 2014 17:40:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WzByL-00007H-LZ for qemu-devel@nongnu.org; Mon, 23 Jun 2014 17:40:26 -0400 Received: from mail-qa0-f44.google.com ([209.85.216.44]:56365) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzByL-00007B-Gf for qemu-devel@nongnu.org; Mon, 23 Jun 2014 17:40:17 -0400 Received: by mail-qa0-f44.google.com with SMTP id hw13so6199804qab.17 for ; Mon, 23 Jun 2014 14:40:17 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1402444514-19658-33-git-send-email-aggelerf@ethz.ch> References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> <1402444514-19658-33-git-send-email-aggelerf@ethz.ch> Date: Mon, 23 Jun 2014 16:40:16 -0500 Message-ID: From: Greg Bellows Content-Type: multipart/alternative; boundary=001a11c24c8e65950404fc87b014 Subject: Re: [Qemu-devel] [PATCH v3 32/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabian Aggeler Cc: Peter Maydell , Peter Crosthwaite , QEMU Developers , Sergey Fedorov , "Edgar E. Iglesias" , Christoffer Dall --001a11c24c8e65950404fc87b014 Content-Type: text/plain; charset=UTF-8 On 10 June 2014 18:55, Fabian Aggeler wrote: > When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) > FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure > and a non-secure instance. > > Signed-off-by: Fabian Aggeler > --- > target-arm/cpu.h | 45 ++++++++++++++++++++++++++++++++++++++++----- > target-arm/helper.c | 27 +++++++++++++++++---------- > 2 files changed, 57 insertions(+), 15 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index c7d606e..13fa966 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -329,11 +329,46 @@ typedef struct CPUARMState { > }; > uint64_t vbar_el2; > uint64_t mvbar; /* (monitor) vector base address register */ > - uint32_t c13_fcse; /* FCSE PID. */ > - uint64_t contextidr_el1; /* Context ID. */ > - uint64_t tpidr_el0; /* User RW Thread register. */ > - uint64_t tpidrro_el0; /* User RO Thread register. */ > - uint64_t tpidr_el1; /* Privileged Thread register. */ > + struct { /* FCSE PID. */ > + uint32_t c13_fcseidr_ns; > + uint32_t c13_fcseidr_s; > + }; > + union { /* Context ID. */ > + struct { > + uint64_t contextidr_ns; > + uint64_t contextidr_s; > + }; > + struct { > + uint64_t contextidr_el1; > + }; > + }; > + union { /* User RW Thread register. */ > + struct { > + uint64_t tpidrurw_ns; > + uint64_t tpidrurw_s; > + }; > + struct { > + uint64_t tpidr_el0; > + }; > + }; > + union { /* User RO Thread register. */ > + struct { > + uint64_t tpidruro_ns; > + uint64_t tpidruro_s; > + }; > + struct { > + uint64_t tpidrro_el0; > + }; > + }; > + union { /* Privileged Thread register. */ > + struct { > + uint64_t tpidrprw_ns; > + uint64_t tpidrprw_s; > + }; > + struct { > + uint64_t tpidr_el1; > + }; > + }; > uint64_t c14_cntfrq; /* Counter Frequency register */ > uint64_t c14_cntkctl; /* Timer Control register */ > ARMGenericTimer c14_timer[NUM_GTIMERS]; > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 2d085aa..aebcc62 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -396,12 +396,15 @@ static const ARMCPRegInfo cp_reginfo[] = { > { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = > 0, > .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, > { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 > = 0, > - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, > cp15.c13_fcse), > + .access = PL1_RW, > + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.c13_fcseidr_s), > + offsetof(CPUARMState, cp15.c13_fcseidr_ns) }, > .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, > { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, > .access = PL1_RW, > - .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1), > + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.contextidr_s), > + offsetof(CPUARMState, cp15.contextidr_ns) }, > .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = > raw_write, }, > REGINFO_SENTINEL > }; > @@ -889,21 +892,25 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { > .access = PL0_RW, > .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = > 0 }, > { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 > = 2, > - .access = PL0_RW, > - .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0), > - .resetfn = arm_cp_reset_ignore }, > + .access = PL0_RW, .resetfn = arm_cp_reset_ignore, > + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), > + offsetoflow32(CPUARMState, cp15.tpidrurw_ns) > } }, > { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, > .access = PL0_R|PL1_W, > .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue > = 0 }, > { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 > = 3, > - .access = PL0_R|PL1_W, > - .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0), > - .resetfn = arm_cp_reset_ignore }, > - { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH, > + .access = PL0_R|PL1_W, .resetfn = arm_cp_reset_ignore, > + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), > + offsetoflow32(CPUARMState, cp15.tpidruro_ns) > } }, > + { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, > .access = PL1_RW, > .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = > 0 }, > + { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 > = 4, > + .access = PL1_RW, .resetfn = arm_cp_reset_ignore, > + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), > + offsetoflow32(CPUARMState, cp15.tpidruro_ns) > } }, > Just discovered that TPIDRPRW is mapped to the wrong storage (tpidruro). Should be mapped to tpidrprw. > REGINFO_SENTINEL > }; > > @@ -4566,7 +4573,7 @@ static inline int get_phys_addr(CPUARMState *env, > target_ulong address, > > /* Fast Context Switch Extension. */ > if (address < 0x02000000) > - address += env->cp15.c13_fcse; > + address += A32_BANKED_CURRENT_REG_GET(env, c13_fcseidr); > > if ((sctlr & SCTLR_M) == 0) { > /* MMU/MPU disabled. */ > -- > 1.8.3.2 > > --001a11c24c8e65950404fc87b014 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable



On 10 June 2014 18:55, Fabian Aggeler <aggelerf@ethz.ch> wrote:
When EL3 is running in Aarch32 (or ARMv7 wit= h Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a non-secure instance.

Signed-off-by: Fabian Aggeler <aggel= erf@ethz.ch>
---
=C2=A0target-arm/cpu.h =C2=A0 =C2=A0| 45 ++++++++++++++++++++++++++++++++++= ++++++-----
=C2=A0target-arm/helper.c | 27 +++++++++++++++++----------
=C2=A02 files changed, 57 insertions(+), 15 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c7d606e..13fa966 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -329,11 +329,46 @@ typedef struct CPUARMState {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t vbar_el2;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t mvbar; /* (monitor) vector base = address register */
- =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t c13_fcse; /* FCSE PID. =C2=A0*/
- =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t contextidr_el1; /* Context ID. =C2=A0= */
- =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t tpidr_el0; /* User RW Thread register= . =C2=A0*/
- =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t tpidrro_el0; /* User RO Thread regist= er. =C2=A0*/
- =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t tpidr_el1; /* Privileged Thread regis= ter. =C2=A0*/
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0struct { /* FCSE PID. */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t c13_fcseidr_ns;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t c13_fcseidr_s;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0union { /* Context ID. */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t contextid= r_ns;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t contextid= r_s;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t contextid= r_el1;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0union { /* User RW Thread register. */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t tpidrurw_= ns;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t tpidrurw_= s;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t tpidr_el0= ;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0union { /* User RO Thread register. */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t tpidruro_= ns;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t tpidruro_= s;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t tpidrro_e= l0;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0union { /* Privileged Thread register. */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t tpidrprw_= ns;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t tpidrprw_= s;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t tpidr_el1= ;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0};
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t c14_cntfrq; /* Counter Frequency= register */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t c14_cntkctl; /* Timer Control re= gister */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ARMGenericTimer c14_timer[NUM_GTIMERS]; diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2d085aa..aebcc62 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -396,12 +396,15 @@ static const ARMCPRegInfo cp_reginfo[] =3D {
=C2=A0 =C2=A0 =C2=A0{ .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0= , .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL0_R, .type =3D ARM_CP_CONST, .rese= tvalue =3D 0 },
=C2=A0 =C2=A0 =C2=A0{ .name =3D "FCSEIDR", .cp =3D 15, .crn =3D 1= 3, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0,
- =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMS= tate, cp15.c13_fcse),
+ =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW,
+ =C2=A0 =C2=A0 =C2=A0.bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.c= 13_fcseidr_s),
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 offsetof(CPUARMState, cp15.c13_fcseidr_ns) },
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0, .writefn =3D fcse_write, .raw= _writefn =3D raw_write, },
=C2=A0 =C2=A0 =C2=A0{ .name =3D "CONTEXTIDR", .state =3D ARM_CP_S= TATE_BOTH,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D = 0, .opc2 =3D 1,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW,
- =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.contextid= r_el1),
+ =C2=A0 =C2=A0 =C2=A0.bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.c= ontextidr_s),
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 offsetof(CPUARMState, cp15.contextidr_ns) },
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0, .writefn =3D contextidr_write= , .raw_writefn =3D raw_write, },
=C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL
=C2=A0};
@@ -889,21 +892,25 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL0_RW,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.tpid= r_el0), .resetvalue =3D 0 },
=C2=A0 =C2=A0 =C2=A0{ .name =3D "TPIDRURW", .cp =3D 15, .crn =3D = 13, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2,
- =C2=A0 =C2=A0 =C2=A0.access =3D PL0_RW,
- =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetoflow32(CPUARMState, cp15.tpid= r_el0),
- =C2=A0 =C2=A0 =C2=A0.resetfn =3D arm_cp_reset_ignore },
+ =C2=A0 =C2=A0 =C2=A0.access =3D PL0_RW, .resetfn =3D arm_cp_reset_ignore,=
+ =C2=A0 =C2=A0 =C2=A0.bank_fieldoffsets =3D { offsetoflow32(CPUARMState, c= p15.tpidrurw_s),
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) } },<= br> =C2=A0 =C2=A0 =C2=A0{ .name =3D "TPIDRRO_EL0", .state =3D ARM_CP_= STATE_AA64,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 3, .crn =3D = 13, .crm =3D 0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL0_R|PL1_W,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.tpid= rro_el0), .resetvalue =3D 0 },
=C2=A0 =C2=A0 =C2=A0{ .name =3D "TPIDRURO", .cp =3D 15, .crn =3D = 13, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 3,
- =C2=A0 =C2=A0 =C2=A0.access =3D PL0_R|PL1_W,
- =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetoflow32(CPUARMState, cp15.tpid= rro_el0),
- =C2=A0 =C2=A0 =C2=A0.resetfn =3D arm_cp_reset_ignore },
- =C2=A0 =C2=A0{ .name =3D "TPIDR_EL1", .state =3D ARM_CP_STATE_B= OTH,
+ =C2=A0 =C2=A0 =C2=A0.access =3D PL0_R|PL1_W, .resetfn =3D arm_cp_reset_ig= nore,
+ =C2=A0 =C2=A0 =C2=A0.bank_fieldoffsets =3D { offsetoflow32(CPUARMState, c= p15.tpidruro_s),
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 offsetoflow32(CPUARMState, cp15.tpidruro_ns) } },<= br> + =C2=A0 =C2=A0{ .name =3D "TPIDR_EL1", .state =3D ARM_CP_STATE_A= A64,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 4, .crn =3D = 13, .crm =3D 0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.tpid= r_el1), .resetvalue =3D 0 },
+ =C2=A0 =C2=A0{ .name =3D "TPIDRPRW", .cp =3D 15, .crn =3D 13, .= crm =3D 0, .opc1 =3D 0, .opc2 =3D 4,
+ =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .resetfn =3D arm_cp_reset_ignore,=
+ =C2=A0 =C2=A0 =C2=A0.bank_fieldoffsets =3D { offsetoflow32(CPUARMState, c= p15.tpidruro_s),
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 offsetoflow32(CPUARMState, cp15.tpidruro_ns) } },<= br>

Just discovered that TPIDRPRW is mapped= to the wrong storage (tpidruro). =C2=A0Should be mapped to tpidrprw.
=C2=A0
=C2=A0 =C2=A0 =C2=A0REGINFO_SENTINEL
=C2=A0};

@@ -4566,7 +4573,7 @@ static inline int get_phys_addr(CPUARMState *env, tar= get_ulong address,

=C2=A0 =C2=A0 =C2=A0/* Fast Context Switch Extension. =C2=A0*/
=C2=A0 =C2=A0 =C2=A0if (address < 0x02000000)
- =C2=A0 =C2=A0 =C2=A0 =C2=A0address +=3D env->cp15.c13_fcse;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0address +=3D A32_BANKED_CURRENT_REG_GET(env, c= 13_fcseidr);

=C2=A0 =C2=A0 =C2=A0if ((sctlr & SCTLR_M) =3D=3D 0) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* MMU/MPU disabled. =C2=A0*/
--
1.8.3.2


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