From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56077) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGBTe-00006N-Sm for qemu-devel@nongnu.org; Tue, 27 Jan 2015 14:07:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YGBTZ-000711-O8 for qemu-devel@nongnu.org; Tue, 27 Jan 2015 14:07:06 -0500 Received: from mail-qc0-f175.google.com ([209.85.216.175]:33697) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGBTZ-00070x-JD for qemu-devel@nongnu.org; Tue, 27 Jan 2015 14:07:01 -0500 Received: by mail-qc0-f175.google.com with SMTP id c9so13592095qcz.6 for ; Tue, 27 Jan 2015 11:07:01 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: <1422029835-4696-1-git-send-email-greg.bellows@linaro.org> <1422029835-4696-5-git-send-email-greg.bellows@linaro.org> Date: Tue, 27 Jan 2015 13:07:01 -0600 Message-ID: From: Greg Bellows Content-Type: multipart/alternative; boundary=001a113a5198afea15050da6f5d1 Subject: Re: [Qemu-devel] [PATCH V2 4/4] target-arm: Add missing SP_ELx register definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers --001a113a5198afea15050da6f5d1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Tue, Jan 27, 2015 at 1:03 PM, Peter Maydell wrote: > On 23 January 2015 at 16:17, Greg Bellows wrote= : > > Added CP register definitions for SP_EL1 and SP_EL2. > > > > Signed-off-by: Greg Bellows > > Reviewed-by: Peter Maydell > > > > --- > > > > v1 -> v2 > > - Remove unnecessary accessfn for SP_EL1/2 > > - Revert SP_EL0 accessfn name to sp_el0_access > > --- > > target-arm/helper.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/target-arm/helper.c b/target-arm/helper.c > > index 29f3b62..79c54a9 100644 > > --- a/target-arm/helper.c > > +++ b/target-arm/helper.c > > @@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { > > .access =3D PL1_RW, .accessfn =3D sp_el0_access, > > .type =3D ARM_CP_NO_MIGRATE, > > .fieldoffset =3D offsetof(CPUARMState, sp_el[0]) }, > > + { .name =3D "SP_EL1", .state =3D ARM_CP_STATE_AA64, > > + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, > > + .access =3D PL2_RW, .type =3D ARM_CP_NO_MIGRATE, > > + .fieldoffset =3D offsetof(CPUARMState, sp_el[1]) }, > > { .name =3D "SPSel", .state =3D ARM_CP_STATE_AA64, > > .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 0, > > .type =3D ARM_CP_NO_MIGRATE, > > @@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = =3D { > > .access =3D PL2_RW, .writefn =3D vbar_write, > > .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[2]), > > .resetvalue =3D 0 }, > > + { .name =3D "SP_EL2", .state =3D ARM_CP_STATE_AA64, > > + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, > > + .access =3D PL3_RW, .type =3D ARM_CP_NO_MIGRATE, > > + .fieldoffset =3D offsetof(CPUARMState, sp_el[2]) }, > > REGINFO_SENTINEL > > }; > > As I was assembling my target-arm queue I found that this patch > and the 'split ARM_CP_NO_MIGRATE' patch semantically conflict; > since this patch happened to be earlier in the queue than that > one, I've resolved this by adding changes to the 'split' patch > which change these ARM_CP_NO_MIGRATE uses to ARM_CP_ALIAS, in > line with how we handled the SP_EL0 regdef. > > thanks > -- PMM > =E2=80=8BThat makes sense.=E2=80=8B --001a113a5198afea15050da6f5d1 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable


On Tue, Jan 27, 2015 at 1:03 PM, Peter Maydell <peter.= maydell@linaro.org> wrote:
=
On 23 January 2015 at 16:17, Greg B= ellows <greg.bellows@linaro.o= rg> wrote:
> Added CP register definitions for SP_EL1 and SP_EL2.
>
> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>
> ---
>
> v1 -> v2
> - Remove unnecessary accessfn for SP_EL1/2
> - Revert SP_EL0 accessfn name to sp_el0_access
> ---
>=C2=A0 target-arm/helper.c | 8 ++++++++
>=C2=A0 1 file changed, 8 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 29f3b62..79c54a9 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2329,6 +2329,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D {=
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 .access =3D PL1_RW, .accessfn =3D sp_el0_ac= cess,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 .fieldoffset =3D offsetof(CPUARMState, sp_e= l[0]) },
> +=C2=A0 =C2=A0 { .name =3D "SP_EL1", .state =3D ARM_CP_STATE= _AA64,
> +=C2=A0 =C2=A0 =C2=A0 .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 1= , .opc2 =3D 0,
> +=C2=A0 =C2=A0 =C2=A0 .access =3D PL2_RW, .type =3D ARM_CP_NO_MIGRATE,=
> +=C2=A0 =C2=A0 =C2=A0 .fieldoffset =3D offsetof(CPUARMState, sp_el[1])= },
>=C2=A0 =C2=A0 =C2=A0 { .name =3D "SPSel", .state =3D ARM_CP_S= TATE_AA64,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm = =3D 2, .opc2 =3D 0,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 .type =3D ARM_CP_NO_MIGRATE,
> @@ -2410,6 +2414,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 .access =3D PL2_RW, .writefn =3D vbar_write= ,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 .fieldoffset =3D offsetof(CPUARMState, cp15= .vbar_el[2]),
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 .resetvalue =3D 0 },
> +=C2=A0 =C2=A0 { .name =3D "SP_EL2", .state =3D ARM_CP_STATE= _AA64,
> +=C2=A0 =C2=A0 =C2=A0 .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 1= , .opc2 =3D 0,
> +=C2=A0 =C2=A0 =C2=A0 .access =3D PL3_RW, .type =3D ARM_CP_NO_MIGRATE,=
> +=C2=A0 =C2=A0 =C2=A0 .fieldoffset =3D offsetof(CPUARMState, sp_el[2])= },
>=C2=A0 =C2=A0 =C2=A0 REGINFO_SENTINEL
>=C2=A0 };

As I was assembling my target-arm queue I found that this patch=
and the 'split ARM_CP_NO_MIGRATE' patch semantically conflict;
since this patch happened to be earlier in the queue than that
one, I've resolved this by adding changes to the 'split' patch<= br> which change these ARM_CP_NO_MIGRATE uses to ARM_CP_ALIAS, in
line with how we handled the SP_EL0 regdef.

thanks
-- PMM

=E2=80=8BThat ma= kes sense.=E2=80=8B

--001a113a5198afea15050da6f5d1--