From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35366) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WvZc6-0006wh-79 for qemu-devel@nongnu.org; Fri, 13 Jun 2014 18:06:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WvZc0-0005Tn-U2 for qemu-devel@nongnu.org; Fri, 13 Jun 2014 18:06:22 -0400 Received: from mail-qa0-f51.google.com ([209.85.216.51]:51597) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WvZc0-0005Tj-Me for qemu-devel@nongnu.org; Fri, 13 Jun 2014 18:06:16 -0400 Received: by mail-qa0-f51.google.com with SMTP id j7so3227654qaq.38 for ; Fri, 13 Jun 2014 15:06:16 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1402444514-19658-29-git-send-email-aggelerf@ethz.ch> References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> <1402444514-19658-29-git-send-email-aggelerf@ethz.ch> Date: Fri, 13 Jun 2014 17:06:15 -0500 Message-ID: From: Greg Bellows Content-Type: multipart/alternative; boundary=001a11c119e2e7437104fbbee28c Subject: Re: [Qemu-devel] [PATCH v3 28/32] target-arm: make DFSR banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabian Aggeler Cc: Peter Maydell , Peter Crosthwaite , QEMU Developers , Sergey Fedorov , "Edgar E. Iglesias" , Christoffer Dall --001a11c119e2e7437104fbbee28c Content-Type: text/plain; charset=UTF-8 I just wanted to point out that the change from array-notation to hard-code numbers in the names undoes Edgar's EL2/EL3 changes. I prefer this way over the array notation. On 10 June 2014 18:55, Fabian Aggeler wrote: > When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) > DFSR has a secure and a non-secure instance. > > Signed-off-by: Fabian Aggeler > --- > target-arm/cpu.h | 13 ++++++++++++- > target-arm/helper-a64.c | 17 ++++++++++++++--- > target-arm/helper.c | 15 ++++++++------- > 3 files changed, 34 insertions(+), 11 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 54c51a4..71782cf 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -266,7 +266,18 @@ typedef struct CPUARMState { > uint32_t ifsr32_el2; > }; > }; > - uint64_t esr_el[4]; > + union { > + struct { > + uint64_t dfsr_ns; > + uint64_t hsr; > + uint64_t dfsr_s; > + }; > + struct { > + uint64_t esr_el1; > + uint64_t esr_el2; > + uint64_t esr_el3; > + }; > + }; > uint32_t c6_region[8]; /* MPU base/size registers. */ > uint64_t far_el[4]; /* Fault address registers. */ > uint64_t par_el1; /* Translation result. */ > diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c > index d7522b6..dbbf012 100644 > --- a/target-arm/helper-a64.c > +++ b/target-arm/helper-a64.c > @@ -447,6 +447,18 @@ void aarch64_cpu_do_interrupt(CPUState *cs) > target_ulong addr = env->cp15.vbar_el[new_el]; > unsigned int new_mode = aarch64_pstate_mode(new_el, true); > int i; > + uint64_t *target_esr; > + switch (new_el) { > + case 3: > + target_esr = &env->cp15.esr_el3; > + break; > + case 2: > + target_esr = &env->cp15.esr_el2; > + break; > + case 1: > + target_esr = &env->cp15.esr_el1; > + break; > + } > > if (arm_current_pl(env) < new_el) { > if (env->aarch64) { > @@ -477,8 +489,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) > case EXCP_SWI: > case EXCP_HVC: > case EXCP_SMC: > - env->cp15.esr_el[new_el] = env->exception.syndrome; > - break; > + *target_esr = env->exception.syndrome; > case EXCP_IRQ: > case EXCP_VIRQ: > addr += 0x80; > @@ -498,7 +509,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) > } else { > env->banked_spsr[0] = cpsr_read(env); > if (!env->thumb) { > - env->cp15.esr_el[new_el] |= 1 << 25; > + *target_esr |= 1 << 25; > } > env->elr_el[new_el] = env->regs[15]; > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index f51498a..793985e 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1492,7 +1492,8 @@ static void vmsa_ttbr_write(CPUARMState *env, const > ARMCPRegInfo *ri, > static const ARMCPRegInfo vmsa_cp_reginfo[] = { > { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, > .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, > - .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), > + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), > + offsetoflow32(CPUARMState, cp15.dfsr_ns) }, > .resetfn = arm_cp_reset_ignore, }, > { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, > .access = PL1_RW, .resetvalue = 0, > @@ -1501,7 +1502,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { > { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, > .access = PL1_RW, > - .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = > 0, }, > + .fieldoffset = offsetof(CPUARMState, cp15.esr_el1), .resetvalue = > 0, }, > { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, > .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, > @@ -1565,7 +1566,7 @@ static void omap_cachemaint_write(CPUARMState *env, > const ARMCPRegInfo *ri, > static const ARMCPRegInfo omap_cp_reginfo[] = { > { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, > .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = > ARM_CP_OVERRIDE, > - .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), > + .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el1), > .resetvalue = 0, }, > { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, > .access = PL1_RW, .type = ARM_CP_NOP }, > @@ -2187,7 +2188,7 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, > - .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, > cp15.esr_el[2]) }, > + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, > cp15.esr_el2) }, > { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, > cp15.far_el[2]) }, > @@ -2299,7 +2300,7 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { > { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_NO_MIGRATE, > .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, > - .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, > cp15.esr_el[3]) }, > + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, > cp15.esr_el3) }, > { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, > .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, > cp15.far_el[3]) }, > @@ -3847,11 +3848,11 @@ void arm_cpu_do_interrupt(CPUState *cs) > offset = 4; > break; > case EXCP_DATA_ABORT: > - env->cp15.esr_el[1] = env->exception.fsr; > + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); > env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32, > env->exception.vaddress); > qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", > - (uint32_t)env->cp15.esr_el[1], > + env->exception.fsr, > (uint32_t)env->exception.vaddress); > new_mode = ARM_CPU_MODE_ABT; > addr = 0x10; > -- > 1.8.3.2 > > --001a11c119e2e7437104fbbee28c Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
I just wanted to point out that the change from array-nota= tion to hard-code numbers in the names undoes Edgar's EL2/EL3 changes. = =C2=A0I prefer this way over the array notation.


On 10 June 2014 18:55, Fabian Aggeler <a= ggelerf@ethz.ch> wrote:
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.

Signed-off-by: Fabian Aggeler <aggel= erf@ethz.ch>
---
=C2=A0target-arm/cpu.h =C2=A0 =C2=A0 =C2=A0 =C2=A0| 13 ++++++++++++-
=C2=A0target-arm/helper-a64.c | 17 ++++++++++++++---
=C2=A0target-arm/helper.c =C2=A0 =C2=A0 | 15 ++++++++-------
=C2=A03 files changed, 34 insertions(+), 11 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 54c51a4..71782cf 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -266,7 +266,18 @@ typedef struct CPUARMState {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t ifsr= 32_el2;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
- =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t esr_el[4];
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0union {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t dfsr_ns;<= br> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t hsr;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t dfsr_s; + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t esr_el1;<= br> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t esr_el2;<= br> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t esr_el3;<= br> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0};
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t c6_region[8]; /* MPU base/size r= egisters. =C2=A0*/
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t far_el[4]; /* Fault address regi= sters. =C2=A0*/
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint64_t par_el1; =C2=A0/* Translation re= sult. */
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index d7522b6..dbbf012 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -447,6 +447,18 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
=C2=A0 =C2=A0 =C2=A0target_ulong addr =3D env->cp15.vbar_el[new_el];
=C2=A0 =C2=A0 =C2=A0unsigned int new_mode =3D aarch64_pstate_mode(new_el, t= rue);
=C2=A0 =C2=A0 =C2=A0int i;
+ =C2=A0 =C2=A0uint64_t *target_esr;
+ =C2=A0 =C2=A0switch (new_el) {
+ =C2=A0 =C2=A0case 3:
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0target_esr =3D &env->cp15.esr_el3;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+ =C2=A0 =C2=A0case 2:
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0target_esr =3D &env->cp15.esr_el2;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+ =C2=A0 =C2=A0case 1:
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0target_esr =3D &env->cp15.esr_el1;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+ =C2=A0 =C2=A0}

=C2=A0 =C2=A0 =C2=A0if (arm_current_pl(env) < new_el) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (env->aarch64) {
@@ -477,8 +489,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
=C2=A0 =C2=A0 =C2=A0case EXCP_SWI:
=C2=A0 =C2=A0 =C2=A0case EXCP_HVC:
=C2=A0 =C2=A0 =C2=A0case EXCP_SMC:
- =C2=A0 =C2=A0 =C2=A0 =C2=A0env->cp15.esr_el[new_el] =3D env->except= ion.syndrome;
- =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0*target_esr =3D env->exception.syndrome; =C2=A0 =C2=A0 =C2=A0case EXCP_IRQ:
=C2=A0 =C2=A0 =C2=A0case EXCP_VIRQ:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0addr +=3D 0x80;
@@ -498,7 +509,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
=C2=A0 =C2=A0 =C2=A0} else {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->banked_spsr[0] =3D cpsr_read(env)= ;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (!env->thumb) {
- =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->cp15.esr_el[new_el] |=3D= 1 << 25;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*target_esr |=3D 1 << 25;<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->elr_el[new_el] =3D env->regs[1= 5];

diff --git a/target-arm/helper.c b/target-arm/helper.c
index f51498a..793985e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1492,7 +1492,8 @@ static void vmsa_ttbr_write(CPUARMState *env, const A= RMCPRegInfo *ri,
=C2=A0static const ARMCPRegInfo vmsa_cp_reginfo[] =3D {
=C2=A0 =C2=A0 =C2=A0{ .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .= crm =3D 0, .opc1 =3D 0, .opc2 =3D 0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .type =3D ARM_CP_NO_MIGRATE,=
- =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetoflow32(CPUARMState, cp15.esr_= el[1]),
+ =C2=A0 =C2=A0 =C2=A0.bank_fieldoffsets =3D { offsetoflow32(CPUARMState, c= p15.dfsr_s),
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 offsetoflow32(CPUARMState, cp15.dfsr_ns) },
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetfn =3D arm_cp_reset_ignore, },
=C2=A0 =C2=A0 =C2=A0{ .name =3D "IFSR", .cp =3D 15, .crn =3D 5, .= crm =3D 0, .opc1 =3D 0, .opc2 =3D 1,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .resetvalue =3D 0,
@@ -1501,7 +1502,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D {
=C2=A0 =C2=A0 =C2=A0{ .name =3D "ESR_EL1", .state =3D ARM_CP_STAT= E_AA64,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0= , .opc2 =3D 0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW,
- =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]= ), .resetvalue =3D 0, },
+ =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetof(CPUARMState, cp15.esr_el1),= .resetvalue =3D 0, },
=C2=A0 =C2=A0 =C2=A0{ .name =3D "TTBR0_EL1", .state =3D ARM_CP_ST= ATE_BOTH,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .writefn =3D vmsa_ttbr_write= , .resetvalue =3D 0,
@@ -1565,7 +1566,7 @@ static void omap_cachemaint_write(CPUARMState *env, c= onst ARMCPRegInfo *ri,
=C2=A0static const ARMCPRegInfo omap_cp_reginfo[] =3D {
=C2=A0 =C2=A0 =C2=A0{ .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .= crm =3D CP_ANY,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D = PL1_RW, .type =3D ARM_CP_OVERRIDE,
- =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetoflow32(CPUARMState, cp15.esr_= el[1]),
+ =C2=A0 =C2=A0 =C2=A0.fieldoffset =3D offsetoflow32(CPUARMState, cp15.esr_= el1),
=C2=A0 =C2=A0 =C2=A0 =C2=A0.resetvalue =3D 0, },
=C2=A0 =C2=A0 =C2=A0{ .name =3D "", .cp =3D 15, .crn =3D 15, .crm= =3D 0, .opc1 =3D 0, .opc2 =3D 0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL1_RW, .type =3D ARM_CP_NOP },
@@ -2187,7 +2188,7 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] =3D { =C2=A0 =C2=A0 =C2=A0{ .name =3D "ESR_EL2", .state =3D ARM_CP_STAT= E_AA64,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.type =3D ARM_CP_NO_MIGRATE,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2= , .opc2 =3D 0,
- =C2=A0 =C2=A0 =C2=A0.access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMS= tate, cp15.esr_el[2]) },
+ =C2=A0 =C2=A0 =C2=A0.access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMS= tate, cp15.esr_el2) },
=C2=A0 =C2=A0 =C2=A0{ .name =3D "FAR_EL2", .state =3D ARM_CP_STAT= E_AA64,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0= , .opc2 =3D 0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL2_RW, .fieldoffset =3D offsetof(CP= UARMState, cp15.far_el[2]) },
@@ -2299,7 +2300,7 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] =3D { =C2=A0 =C2=A0 =C2=A0{ .name =3D "ESR_EL3", .state =3D ARM_CP_STAT= E_AA64,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.type =3D ARM_CP_NO_MIGRATE,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 2= , .opc2 =3D 0,
- =C2=A0 =C2=A0 =C2=A0.access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMS= tate, cp15.esr_el[3]) },
+ =C2=A0 =C2=A0 =C2=A0.access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMS= tate, cp15.esr_el3) },
=C2=A0 =C2=A0 =C2=A0{ .name =3D "FAR_EL3", .state =3D ARM_CP_STAT= E_AA64,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0= , .opc2 =3D 0,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.access =3D PL3_RW, .fieldoffset =3D offsetof(CP= UARMState, cp15.far_el[3]) },
@@ -3847,11 +3848,11 @@ void arm_cpu_do_interrupt(CPUState *cs)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0offset =3D 4;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
=C2=A0 =C2=A0 =C2=A0case EXCP_DATA_ABORT:
- =C2=A0 =C2=A0 =C2=A0 =C2=A0env->cp15.esr_el[1] =3D env->exception.f= sr;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0A32_BANKED_CURRENT_REG_SET(env, dfsr, env->= exception.fsr);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->cp15.far_el[1] =3D deposit64(env-= >cp15.far_el[1], 0, 32,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0en= v->exception.vaddress);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_log_mask(CPU_LOG_INT, "...with = DFSR 0x%x DFAR 0x%x\n",
- =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0(uint32_t)env->cp15.esr_el[1],
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0env->exception.fsr,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0(uint32_t)env->exception.vaddress);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0new_mode =3D ARM_CPU_MODE_ABT;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0addr =3D 0x10;
--
1.8.3.2


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