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From: Greg Bellows <greg.bellows@linaro.org>
To: Aggeler Fabian <aggelerf@student.ethz.ch>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Sergey Fedorov <serge.fdrv@gmail.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	Christoffer Dall <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v3 05/32] target-arm: reject switching to monitor mode
Date: Tue, 24 Jun 2014 08:43:38 -0500	[thread overview]
Message-ID: <CAOgzsHVkOucejEw=Pvi1ifBjjV6mgxORv+fsdeYonOApfiHw0A@mail.gmail.com> (raw)
In-Reply-To: <51C477A1-ADE4-4308-8B97-075E782EE815@ethz.ch>

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Thanks.

I wont bother making a change to your patchset for this and will revisit
after things are upstream if a change is needed.

Greg


On 24 June 2014 07:19, Aggeler Fabian <aggelerf@student.ethz.ch> wrote:

> Hm…yes, this case is missing, but it is only missing for ARMv7 as this bit
> is RES0 in ARMv8. Even in ARMv7 it is IMPDEF whether
> this bit is supported. And since ARMv7 mentions, that this bit is
> deprecated from the introduction of Virtualization Extensions
> I did not care to add this special case.
>
> On 12 Jun 2014, at 23:55, Greg Bellows <greg.bellows@linaro.org<mailto:
> greg.bellows@linaro.org>> wrote:
>
> Missing case where it is UNPREDICTABLE to enter FIQ mode from non-secure
> state if NSACR.RFR is 1.
>
>
> On 10 June 2014 18:54, Fabian Aggeler <aggelerf@ethz.ch<mailto:
> aggelerf@ethz.ch>> wrote:
> From: Sergey Fedorov <s.fedorov@samsung.com<mailto:s.fedorov@samsung.com>>
>
> ...from non-secure state.
>
> Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com<mailto:
> s.fedorov@samsung.com>>
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch<mailto:aggelerf@ethz.ch>>
> ---
>  target-arm/helper.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index d8d6637..ace8d8b 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3049,6 +3049,8 @@ static int bad_mode_switch(CPUARMState *env, int
> mode)
>      case ARM_CPU_MODE_IRQ:
>      case ARM_CPU_MODE_FIQ:
>          return 0;
> +    case ARM_CPU_MODE_MON:
> +        return !arm_is_secure(env);
>      default:
>          return 1;
>      }
> --
> 1.8.3.2
>
>
>
>

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  reply	other threads:[~2014-06-24 13:43 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-10 23:54 [Qemu-devel] [PATCH v3 00/32] target-arm: add Security Extensions for CPUs Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 01/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 02/32] target-arm: move Aarch32 SCR into security reglist Fabian Aggeler
2014-06-12 21:55   ` Greg Bellows
2014-06-17  7:22     ` Aggeler  Fabian
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 03/32] target-arm: increase arrays of registers R13 & R14 Fabian Aggeler
2014-06-17  8:57   ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function Fabian Aggeler
2014-06-11 12:17   ` Sergey Fedorov
2014-06-12 16:26     ` Greg Bellows
2014-06-12 17:26       ` Sergey Fedorov
2014-06-12 18:35         ` Greg Bellows
2014-06-12 19:09           ` Sergey Fedorov
2014-06-17  5:51   ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 05/32] target-arm: reject switching to monitor mode Fabian Aggeler
2014-06-12 21:55   ` Greg Bellows
2014-06-24 12:19     ` Aggeler  Fabian
2014-06-24 13:43       ` Greg Bellows [this message]
2014-06-17  5:43   ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 06/32] target-arm: make arm_current_pl() return PL3 Fabian Aggeler
2014-06-17  5:40   ` Edgar E. Iglesias
2014-06-17  7:12     ` Aggeler  Fabian
2014-06-17  7:07       ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 07/32] target-arm: add non-secure Translation Block flag Fabian Aggeler
2014-06-17  9:15   ` Edgar E. Iglesias
2014-06-17 10:07     ` Sergey Fedorov
2014-06-19  5:30       ` Edgar E. Iglesias
2014-06-25  4:15   ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 08/32] target-arm: A32: Emulate the SMC instruction Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 09/32] target-arm: extend Aarch32 async excp masking Fabian Aggeler
2014-06-17  7:48   ` Edgar E. Iglesias
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 10/32] target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling Fabian Aggeler
2014-06-12 21:55   ` Greg Bellows
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 11/32] target-arm: add async excp target_el&mode function Fabian Aggeler
2014-06-12 21:56   ` Greg Bellows
2014-06-17  7:29     ` Aggeler  Fabian
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 12/32] target-arm: use dedicated target_el function Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 13/32] target-arm: implement IRQ/FIQ routing to Monitor mode Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 14/32] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI Fabian Aggeler
2014-06-12 22:43   ` Greg Bellows
2014-06-17  7:36     ` Aggeler  Fabian
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 15/32] target-arm: add NSACR register Fabian Aggeler
2014-06-13 18:27   ` Greg Bellows
2014-06-17  7:41     ` Aggeler  Fabian
2014-06-24 15:37       ` Greg Bellows
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 16/32] target-arm: add SDER definition Fabian Aggeler
2014-06-10 23:54 ` [Qemu-devel] [PATCH v3 17/32] target-arm: add MVBAR support Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 18/32] target-arm: add macros to access banked registers Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 19/32] target-arm: insert Aarch32 cpregs twice into hashtable Fabian Aggeler
2014-06-12 19:49   ` Sergey Fedorov
2014-06-25  5:20   ` Edgar E. Iglesias
2014-06-25 13:50     ` Greg Bellows
2014-06-26  3:56       ` Edgar E. Iglesias
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 20/32] target-arm: arrayfying fieldoffset for banking Fabian Aggeler
2014-06-13 20:18   ` Greg Bellows
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 21/32] target-arm: add SCTLR_EL3 and make SCTLR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 22/32] target-arm: make CSSELR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 23/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 24/32] target-arm: add TCR_EL3 and make TTBCR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 25/32] target-arm: make c2_mask and c2_base_mask banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 26/32] target-arm: make DACR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 27/32] target-arm: make IFSR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 28/32] target-arm: make DFSR banked Fabian Aggeler
2014-06-13 22:06   ` Greg Bellows
2014-06-17  6:12     ` Edgar E. Iglesias
2014-06-23 16:53       ` Greg Bellows
2014-06-24 11:05       ` Aggeler  Fabian
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 29/32] target-arm: make IFAR/DFAR banked Fabian Aggeler
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 30/32] target-arm: make PAR banked Fabian Aggeler
2014-06-13 22:49   ` Greg Bellows
2014-06-17  7:15     ` Aggeler  Fabian
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 31/32] target-arm: make VBAR banked Fabian Aggeler
2014-06-13 22:43   ` Greg Bellows
2014-06-17  7:17     ` Aggeler  Fabian
2014-06-10 23:55 ` [Qemu-devel] [PATCH v3 32/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) Fabian Aggeler
2014-06-23 21:40   ` Greg Bellows
2014-06-24 11:08     ` Aggeler  Fabian
2014-06-11  1:31 ` [Qemu-devel] [PATCH v3 00/32] target-arm: add Security Extensions for CPUs Edgar E. Iglesias

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