From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60967) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YFqJ0-00068w-TC for qemu-devel@nongnu.org; Mon, 26 Jan 2015 15:30:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YFqIy-0005OA-2b for qemu-devel@nongnu.org; Mon, 26 Jan 2015 15:30:42 -0500 Received: from mail-qc0-f177.google.com ([209.85.216.177]:52877) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YFqIx-0005O2-TT for qemu-devel@nongnu.org; Mon, 26 Jan 2015 15:30:39 -0500 Received: by mail-qc0-f177.google.com with SMTP id p6so8915938qcv.8 for ; Mon, 26 Jan 2015 12:30:39 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <1422037228-5363-8-git-send-email-peter.maydell@linaro.org> References: <1422037228-5363-1-git-send-email-peter.maydell@linaro.org> <1422037228-5363-8-git-send-email-peter.maydell@linaro.org> Date: Mon, 26 Jan 2015 14:30:39 -0600 Message-ID: From: Greg Bellows Content-Type: multipart/alternative; boundary=047d7b5d430ef3a217050d940269 Subject: Re: [Qemu-devel] [PATCH 07/11] target-arm: Split AArch64 cases out of ats_write() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: "Edgar E. Iglesias" , Andrew Jones , =?UTF-8?B?QWxleCBCZW5uw6ll?= , QEMU Developers , Patch Tracking --047d7b5d430ef3a217050d940269 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Fri, Jan 23, 2015 at 12:20 PM, Peter Maydell wrote: > Instead of simply reusing ats_write() as the handler for both AArch32 > and AArch64 address translation operations, use a different function > for each with the common code in a third function. This is necessary > because the semantics for selecting the right translation regime are > different; we are only getting away with sharing currently because > we don't support EL2 and only support EL3 in AArch32. > > Signed-off-by: Peter Maydell > --- > target-arm/helper.c | 33 ++++++++++++++++++++++++++------- > 1 file changed, 26 insertions(+), 7 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 06478d8..04bc0a1 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1435,13 +1435,13 @@ static CPAccessResult ats_access(CPUARMState *env= , > const ARMCPRegInfo *ri) > return CP_ACCESS_OK; > } > > -static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t > value) > +static uint64_t do_ats_write(CPUARMState *env, uint64_t value, > + int access_type, int is_user) > { > hwaddr phys_addr; > target_ulong page_size; > int prot; > - int ret, is_user =3D ri->opc2 & 2; > - int access_type =3D ri->opc2 & 1; > + int ret; > uint64_t par64; > > ret =3D get_phys_addr(env, value, access_type, is_user, > @@ -1481,9 +1481,28 @@ static void ats_write(CPUARMState *env, const > ARMCPRegInfo *ri, uint64_t value) > ((ret & 0xf) << 1) | 1; > } > } > + return par64; > +} > + > +static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t > value) > +{ > + int is_user =3D ri->opc2 & 2; > + int access_type =3D ri->opc2 & 1; > + uint64_t par64; > + > + par64 =3D do_ats_write(env, value, access_type, is_user); > > A32_BANKED_CURRENT_REG_SET(env, par, par64); > } > + > +static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, > + uint64_t value) > +{ > + int is_user =3D ri->opc2 & 2; > + int access_type =3D ri->opc2 & 1; > + > + env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, is_use= r); > +} > #endif > > static const ARMCPRegInfo vapa_cp_reginfo[] =3D { > @@ -2257,16 +2276,16 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { > /* 64 bit address translation operations */ > { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, > .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, > - .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writefn =3D ats_w= rite }, > + .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writefn =3D ats_w= rite64 > }, > { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, > .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, > - .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writefn =3D ats_w= rite }, > + .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writefn =3D ats_w= rite64 > }, > { .name =3D "AT_S1E0R", .state =3D ARM_CP_STATE_AA64, > .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 2, > - .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writefn =3D ats_w= rite }, > + .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writefn =3D ats_w= rite64 > }, > { .name =3D "AT_S1E0W", .state =3D ARM_CP_STATE_AA64, > .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 3, > - .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writefn =3D ats_w= rite }, > + .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writefn =3D ats_w= rite64 > }, > #endif > /* TLB invalidate last level of translation table walk */ > { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, > .opc2 =3D 5, > -- > 1.9.1 > > =E2=80=8BReviewed-by: Greg Bellows =E2=80=8B --047d7b5d430ef3a217050d940269 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable


On Fri, Jan 23, 2015 at 12:20 PM, Peter Maydell <peter= .maydell@linaro.org> wrote:
Instead of simply reusing ats_write() as the handler for both AArch32
and AArch64 address translation operations, use a different function
for each with the common code in a third function. This is necessary
because the semantics for selecting the right translation regime are
different; we are only getting away with sharing currently because
we don't support EL2 and only support EL3 in AArch32.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
=C2=A0target-arm/helper.c | 33 ++++++++++++++++++++++++++-------
=C2=A01 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 06478d8..04bc0a1 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1435,13 +1435,13 @@ static CPAccessResult ats_access(CPUARMState *env, = const ARMCPRegInfo *ri)
=C2=A0 =C2=A0 =C2=A0return CP_ACCESS_OK;
=C2=A0}

-static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue)
+static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int access_type, int is_user)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0hwaddr phys_addr;
=C2=A0 =C2=A0 =C2=A0target_ulong page_size;
=C2=A0 =C2=A0 =C2=A0int prot;
-=C2=A0 =C2=A0 int ret, is_user =3D ri->opc2 & 2;
-=C2=A0 =C2=A0 int access_type =3D ri->opc2 & 1;
+=C2=A0 =C2=A0 int ret;
=C2=A0 =C2=A0 =C2=A0uint64_t par64;

=C2=A0 =C2=A0 =C2=A0ret =3D get_phys_addr(env, value, access_type, is_user,=
@@ -1481,9 +1481,28 @@ static void ats_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0((ret & 0xf) << 1) | 1;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
=C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 return par64;
+}
+
+static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue)
+{
+=C2=A0 =C2=A0 int is_user =3D ri->opc2 & 2;
+=C2=A0 =C2=A0 int access_type =3D ri->opc2 & 1;
+=C2=A0 =C2=A0 uint64_t par64;
+
+=C2=A0 =C2=A0 par64 =3D do_ats_write(env, value, access_type, is_user);
=C2=A0 =C2=A0 =C2=A0A32_BANKED_CURRENT_REG_SET(env, par, par64);
=C2=A0}
+
+static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 uint64_t value)
+{
+=C2=A0 =C2=A0 int is_user =3D ri->opc2 & 2;
+=C2=A0 =C2=A0 int access_type =3D ri->opc2 & 1;
+
+=C2=A0 =C2=A0 env->cp15.par_el[1] =3D do_ats_write(env, value, access_t= ype, is_user);
+}
=C2=A0#endif

=C2=A0static const ARMCPRegInfo vapa_cp_reginfo[] =3D {
@@ -2257,16 +2276,16 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D {
=C2=A0 =C2=A0 =C2=A0/* 64 bit address translation operations */
=C2=A0 =C2=A0 =C2=A0{ .name =3D "AT_S1E1R", .state =3D ARM_CP_STA= TE_AA64,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8= , .opc2 =3D 0,
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writ= efn =3D ats_write },
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writ= efn =3D ats_write64 },
=C2=A0 =C2=A0 =C2=A0{ .name =3D "AT_S1E1W", .state =3D ARM_CP_STA= TE_AA64,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8= , .opc2 =3D 1,
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writ= efn =3D ats_write },
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writ= efn =3D ats_write64 },
=C2=A0 =C2=A0 =C2=A0{ .name =3D "AT_S1E0R", .state =3D ARM_CP_STA= TE_AA64,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8= , .opc2 =3D 2,
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writ= efn =3D ats_write },
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writ= efn =3D ats_write64 },
=C2=A0 =C2=A0 =C2=A0{ .name =3D "AT_S1E0W", .state =3D ARM_CP_STA= TE_AA64,
=C2=A0 =C2=A0 =C2=A0 =C2=A0.opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8= , .opc2 =3D 3,
-=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writ= efn =3D ats_write },
+=C2=A0 =C2=A0 =C2=A0 .access =3D PL1_W, .type =3D ARM_CP_NO_MIGRATE, .writ= efn =3D ats_write64 },
=C2=A0#endif
=C2=A0 =C2=A0 =C2=A0/* TLB invalidate last level of translation table walk = */
=C2=A0 =C2=A0 =C2=A0{ .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 = =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5,
--
1.9.1


= =E2=80=8BReviewed-by: Greg Bellows <greg.bellows@linaro.org>=E2=80=8B

--047d7b5d430ef3a217050d940269--