From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45945) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YFrQ3-0000af-9U for qemu-devel@nongnu.org; Mon, 26 Jan 2015 16:42:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YFrPz-0002J9-Ou for qemu-devel@nongnu.org; Mon, 26 Jan 2015 16:42:03 -0500 Received: from mail-qg0-f44.google.com ([209.85.192.44]:36015) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YFrPz-0002Ix-I9 for qemu-devel@nongnu.org; Mon, 26 Jan 2015 16:41:59 -0500 Received: by mail-qg0-f44.google.com with SMTP id l89so9060326qgf.3 for ; Mon, 26 Jan 2015 13:41:59 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <1422037228-5363-9-git-send-email-peter.maydell@linaro.org> References: <1422037228-5363-1-git-send-email-peter.maydell@linaro.org> <1422037228-5363-9-git-send-email-peter.maydell@linaro.org> Date: Mon, 26 Jan 2015 15:41:59 -0600 Message-ID: From: Greg Bellows Content-Type: multipart/alternative; boundary=047d7b5d430e0ad871050d9502c3 Subject: Re: [Qemu-devel] [PATCH 08/11] target-arm: Pass mmu_idx to get_phys_addr() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: "Edgar E. Iglesias" , Andrew Jones , =?UTF-8?B?QWxleCBCZW5uw6ll?= , QEMU Developers , Patch Tracking --047d7b5d430e0ad871050d9502c3 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Fri, Jan 23, 2015 at 12:20 PM, Peter Maydell wrote: > Make all the callers of get_phys_addr() pass it the correct > mmu_idx rather than just a simple "is_user" flag. This includes > properly decoding the AT/ATS system instructions; we include the > logic for handling all the opc1/opc2 cases because we'll need > them later for supporting EL2/EL3, even if we don't have the > regdef stanzas yet. > > Signed-off-by: Peter Maydell > --- > target-arm/helper.c | 110 > +++++++++++++++++++++++++++++++++++++++++++++------- > 1 file changed, 96 insertions(+), 14 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 04bc0a1..0ae04eb 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -13,7 +13,7 @@ > > #ifndef CONFIG_USER_ONLY > static inline int get_phys_addr(CPUARMState *env, target_ulong address, > - int access_type, int is_user, > + int access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, int *prot, > target_ulong *page_size); > > @@ -1436,7 +1436,7 @@ static CPAccessResult ats_access(CPUARMState *env, > const ARMCPRegInfo *ri) > } > > static uint64_t do_ats_write(CPUARMState *env, uint64_t value, > - int access_type, int is_user) > + int access_type, ARMMMUIdx mmu_idx) > { > hwaddr phys_addr; > target_ulong page_size; > @@ -1444,7 +1444,7 @@ static uint64_t do_ats_write(CPUARMState *env, > uint64_t value, > int ret; > uint64_t par64; > > - ret =3D get_phys_addr(env, value, access_type, is_user, > + ret =3D get_phys_addr(env, value, access_type, mmu_idx, > &phys_addr, &prot, &page_size); > if (extended_addresses_enabled(env)) { > /* ret is a DFSR/IFSR value for the long descriptor > @@ -1486,11 +1486,58 @@ static uint64_t do_ats_write(CPUARMState *env, > uint64_t value, > > static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t > value) > { > - int is_user =3D ri->opc2 & 2; > int access_type =3D ri->opc2 & 1; > uint64_t par64; > + ARMMMUIdx mmu_idx; > + int el =3D arm_current_el(env); > + bool secure =3D arm_is_secure_below_el3(env); > > - par64 =3D do_ats_write(env, value, access_type, is_user); > + switch (ri->opc2 & 6) { > + case 0: > + /* stage 1 current state PL1 */ > + switch (el) { > + case 3: > + mmu_idx =3D ARMMMUIdx_S1E3; > + break; > + case 2: > + mmu_idx =3D ARMMMUIdx_S1NSE1; > + break; > + case 1: > + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; > + break; > + default: > + g_assert_not_reached(); > + } > + break; > + case 2: > + /* stage 1 current state PL0 */ > + switch (el) { > + case 3: > + mmu_idx =3D ARMMMUIdx_S1SE0; > + break; > + case 2: > + mmu_idx =3D ARMMMUIdx_S1NSE0; > + break; > + case 1: > + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; > + break; > + default: > + g_assert_not_reached(); > + } > + break; > + case 4: > + /* stage 1+2 NonSecure PL1 */ > + mmu_idx =3D ARMMMUIdx_S12NSE1; > + break; > + case 6: > + /* stage 1+2 NonSecure PL0 */ > + mmu_idx =3D ARMMMUIdx_S12NSE0; > + break; > + default: > + g_assert_not_reached(); > + } > + > + par64 =3D do_ats_write(env, value, access_type, mmu_idx); > > A32_BANKED_CURRENT_REG_SET(env, par, par64); > } > @@ -1498,10 +1545,40 @@ static void ats_write(CPUARMState *env, const > ARMCPRegInfo *ri, uint64_t value) > static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - int is_user =3D ri->opc2 & 2; > int access_type =3D ri->opc2 & 1; > + ARMMMUIdx mmu_idx; > + int secure =3D arm_is_secure_below_el3(env); > + > + switch (ri->opc2 & 6) { > + case 0: > + switch (ri->opc1) { > + case 0: > + mmu_idx =3D secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; > + break; > + case 4: > + mmu_idx =3D ARMMMUIdx_S1E2; > + break; > + case 6: > + mmu_idx =3D ARMMMUIdx_S1E3; > + break; > + default: > + g_assert_not_reached(); > + } > + break; > + case 2: > + mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; > + break; > + case 4: > + mmu_idx =3D ARMMMUIdx_S12NSE1; > + break; > + case 6: > + mmu_idx =3D ARMMMUIdx_S12NSE0; > + break; > + default: > + g_assert_not_reached(); > + } > =E2=80=8BThe above cases would be more readable if each case had a comment identifying the corresponding AT instruction. Just faster for reference purposes. > > - env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, is_use= r); > + env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_id= x); > } > #endif > > @@ -5084,13 +5161,13 @@ static int get_phys_addr_mpu(CPUARMState *env, > uint32_t address, > * @env: CPUARMState > * @address: virtual address to get physical address for > * @access_type: 0 for read, 1 for write, 2 for execute > - * @is_user: 0 for privileged access, 1 for user > + * @mmu_idx: MMU index indicating required translation regime > * @phys_ptr: set to the physical address corresponding to the virtual > address > * @prot: set to the permissions for the page containing phys_ptr > * @page_size: set to the size of the page containing phys_ptr > */ > static inline int get_phys_addr(CPUARMState *env, target_ulong address, > - int access_type, int is_user, > + int access_type, ARMMMUIdx mmu_idx, > hwaddr *phys_ptr, int *prot, > target_ulong *page_size) > { > @@ -5099,6 +5176,11 @@ static inline int get_phys_addr(CPUARMState *env, > target_ulong address, > */ > uint32_t sctlr =3D A32_BANKED_CURRENT_REG_GET(env, sctlr); > > + /* This will go away when we handle mmu_idx properly here */ > + int is_user =3D (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || > + mmu_idx =3D=3D ARMMMUIdx_S1SE0 || > + mmu_idx =3D=3D ARMMMUIdx_S1NSE0); > + > /* Fast Context Switch Extension. */ > if (address < 0x02000000) { > address +=3D A32_BANKED_CURRENT_REG_GET(env, fcseidr); > @@ -5134,13 +5216,11 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr > address, > hwaddr phys_addr; > target_ulong page_size; > int prot; > - int ret, is_user; > + int ret; > uint32_t syn; > bool same_el =3D (arm_current_el(env) !=3D 0); > > - /* TODO: pass the translation regime to get_phys_addr */ > - is_user =3D (arm_mmu_idx_to_el(mmu_idx) =3D=3D 0); > - ret =3D get_phys_addr(env, address, access_type, is_user, &phys_addr= , > &prot, > + ret =3D get_phys_addr(env, address, access_type, mmu_idx, &phys_addr= , > &prot, > &page_size); > if (ret =3D=3D 0) { > /* Map a single [sub]page. */ > @@ -5176,12 +5256,14 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr > address, > hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) > { > ARMCPU *cpu =3D ARM_CPU(cs); > + CPUARMState *env =3D &cpu->env; > hwaddr phys_addr; > target_ulong page_size; > int prot; > int ret; > > - ret =3D get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, > &page_size); > + ret =3D get_phys_addr(env, addr, 0, cpu_mmu_index(env), &phys_addr, > + &prot, &page_size); > > if (ret !=3D 0) { > return -1; > -- > 1.9.1 > > > =E2=80=8BOtherwise, Reviewed-by: Greg Bellows =E2=80=8B --047d7b5d430e0ad871050d9502c3 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable


On Fri, Jan 23, 2015 at 12:20 PM, Peter Maydell <peter= .maydell@linaro.org> wrote:
Make all the callers of get_phys_addr() pass it the correct
mmu_idx rather than just a simple "is_user" flag. This includes properly decoding the AT/ATS system instructions; we include the
logic for handling all the opc1/opc2 cases because we'll need
them later for supporting EL2/EL3, even if we don't have the
regdef stanzas yet.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
=C2=A0target-arm/helper.c | 110 +++++++++++++++++++++++++++++++++++++++++++= ++-------
=C2=A01 file changed, 96 insertions(+), 14 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 04bc0a1..0ae04eb 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -13,7 +13,7 @@

=C2=A0#ifndef CONFIG_USER_ONLY
=C2=A0static inline int get_phys_addr(CPUARMState *env, target_ulong addres= s,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int access_type, int is_user,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int access_type, ARMMMUIdx mmu_idx,<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hwaddr *phys_ptr, int *prot, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *page_size);

@@ -1436,7 +1436,7 @@ static CPAccessResult ats_access(CPUARMState *env, co= nst ARMCPRegInfo *ri)
=C2=A0}

=C2=A0static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int access_type, int is_user)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int access_type, ARMMMUIdx mmu_idx)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0hwaddr phys_addr;
=C2=A0 =C2=A0 =C2=A0target_ulong page_size;
@@ -1444,7 +1444,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value,
=C2=A0 =C2=A0 =C2=A0int ret;
=C2=A0 =C2=A0 =C2=A0uint64_t par64;

-=C2=A0 =C2=A0 ret =3D get_phys_addr(env, value, access_type, is_user,
+=C2=A0 =C2=A0 ret =3D get_phys_addr(env, value, access_type, mmu_idx,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0&phys_addr, &prot, &page_size);
=C2=A0 =C2=A0 =C2=A0if (extended_addresses_enabled(env)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* ret is a DFSR/IFSR value for the long = descriptor
@@ -1486,11 +1486,58 @@ static uint64_t do_ats_write(CPUARMState *env, uint= 64_t value,

=C2=A0static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint6= 4_t value)
=C2=A0{
-=C2=A0 =C2=A0 int is_user =3D ri->opc2 & 2;
=C2=A0 =C2=A0 =C2=A0int access_type =3D ri->opc2 & 1;
=C2=A0 =C2=A0 =C2=A0uint64_t par64;
+=C2=A0 =C2=A0 ARMMMUIdx mmu_idx;
+=C2=A0 =C2=A0 int el =3D arm_current_el(env);
+=C2=A0 =C2=A0 bool secure =3D arm_is_secure_below_el3(env);

-=C2=A0 =C2=A0 par64 =3D do_ats_write(env, value, access_type, is_user); +=C2=A0 =C2=A0 switch (ri->opc2 & 6) {
+=C2=A0 =C2=A0 case 0:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* stage 1 current state PL1 */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 switch (el) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 case 3:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D ARMMMUIdx_S1E3;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 case 2:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D ARMMMUIdx_S1NSE1; +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 case 1:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D secure ? ARMMMUIdx_S= 1SE1 : ARMMMUIdx_S1NSE1;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 g_assert_not_reached();
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 2:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* stage 1 current state PL0 */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 switch (el) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 case 3:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D ARMMMUIdx_S1SE0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 case 2:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D ARMMMUIdx_S1NSE0; +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 case 1:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D secure ? ARMMMUIdx_S= 1SE0 : ARMMMUIdx_S1NSE0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 g_assert_not_reached();
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 4:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* stage 1+2 NonSecure PL1 */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D ARMMMUIdx_S12NSE1;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 6:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* stage 1+2 NonSecure PL0 */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D ARMMMUIdx_S12NSE0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 g_assert_not_reached();
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 par64 =3D do_ats_write(env, value, access_type, mmu_idx);
=C2=A0 =C2=A0 =C2=A0A32_BANKED_CURRENT_REG_SET(env, par, par64);
=C2=A0}
@@ -1498,10 +1545,40 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value)
=C2=A0static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0uint64_t value)
=C2=A0{
-=C2=A0 =C2=A0 int is_user =3D ri->opc2 & 2;
=C2=A0 =C2=A0 =C2=A0int access_type =3D ri->opc2 & 1;
+=C2=A0 =C2=A0 ARMMMUIdx mmu_idx;
+=C2=A0 =C2=A0 int secure =3D arm_is_secure_below_el3(env);
+
+=C2=A0 =C2=A0 switch (ri->opc2 & 6) {
+=C2=A0 =C2=A0 case 0:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 switch (ri->opc1) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 case 0:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D secure ? ARMMMUIdx_S= 1SE1 : ARMMMUIdx_S1NSE1;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 case 4:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D ARMMMUIdx_S1E2;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 case 6:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D ARMMMUIdx_S1E3;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 g_assert_not_reached();
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 2:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D secure ? ARMMMUIdx_S1SE0 : ARMMMUI= dx_S1NSE0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 4:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D ARMMMUIdx_S12NSE1;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case 6:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 mmu_idx =3D ARMMMUIdx_S12NSE0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 g_assert_not_reached();
+=C2=A0 =C2=A0 }

=E2=80=8BThe above = cases would be more readable if each case had a comment identifying the cor= responding AT instruction.=C2=A0 Just faster for reference purposes.
<= /div>
=C2=A0

-=C2=A0 =C2=A0 env->cp15.par_el[1] =3D do_ats_write(env, value, access_t= ype, is_user);
+=C2=A0 =C2=A0 env->cp15.par_el[1] =3D do_ats_write(env, value, access_t= ype, mmu_idx);
=C2=A0}
=C2=A0#endif

@@ -5084,13 +5161,13 @@ static int get_phys_addr_mpu(CPUARMState *env, uint= 32_t address,
=C2=A0 * @env: CPUARMState
=C2=A0 * @address: virtual address to get physical address for
=C2=A0 * @access_type: 0 for read, 1 for write, 2 for execute
- * @is_user: 0 for privileged access, 1 for user
+ * @mmu_idx: MMU index indicating required translation regime
=C2=A0 * @phys_ptr: set to the physical address corresponding to the virtua= l address
=C2=A0 * @prot: set to the permissions for the page containing phys_ptr
=C2=A0 * @page_size: set to the size of the page containing phys_ptr
=C2=A0 */
=C2=A0static inline int get_phys_addr(CPUARMState *env, target_ulong addres= s,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int access_type, int is_user,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int access_type, ARMMMUIdx mmu_idx,<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hwaddr *phys_ptr, int *prot, =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *page_size)
=C2=A0{
@@ -5099,6 +5176,11 @@ static inline int get_phys_addr(CPUARMState *env, ta= rget_ulong address,
=C2=A0 =C2=A0 =C2=A0 */
=C2=A0 =C2=A0 =C2=A0uint32_t sctlr =3D A32_BANKED_CURRENT_REG_GET(env, sctl= r);

+=C2=A0 =C2=A0 /* This will go away when we handle mmu_idx properly here */=
+=C2=A0 =C2=A0 int is_user =3D (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 ||
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mmu_i= dx =3D=3D ARMMMUIdx_S1SE0 ||
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mmu_i= dx =3D=3D ARMMMUIdx_S1NSE0);
+
=C2=A0 =C2=A0 =C2=A0/* Fast Context Switch Extension.=C2=A0 */
=C2=A0 =C2=A0 =C2=A0if (address < 0x02000000) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0address +=3D A32_BANKED_CURRENT_REG_GET(e= nv, fcseidr);
@@ -5134,13 +5216,11 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress,
=C2=A0 =C2=A0 =C2=A0hwaddr phys_addr;
=C2=A0 =C2=A0 =C2=A0target_ulong page_size;
=C2=A0 =C2=A0 =C2=A0int prot;
-=C2=A0 =C2=A0 int ret, is_user;
+=C2=A0 =C2=A0 int ret;
=C2=A0 =C2=A0 =C2=A0uint32_t syn;
=C2=A0 =C2=A0 =C2=A0bool same_el =3D (arm_current_el(env) !=3D 0);

-=C2=A0 =C2=A0 /* TODO: pass the translation regime to get_phys_addr */
-=C2=A0 =C2=A0 is_user =3D (arm_mmu_idx_to_el(mmu_idx) =3D=3D 0);
-=C2=A0 =C2=A0 ret =3D get_phys_addr(env, address, access_type, is_user, &a= mp;phys_addr, &prot,
+=C2=A0 =C2=A0 ret =3D get_phys_addr(env, address, access_type, mmu_idx, &a= mp;phys_addr, &prot,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0&page_size);
=C2=A0 =C2=A0 =C2=A0if (ret =3D=3D 0) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Map a single [sub]page.=C2=A0 */
@@ -5176,12 +5256,14 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress,
=C2=A0hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0ARMCPU *cpu =3D ARM_CPU(cs);
+=C2=A0 =C2=A0 CPUARMState *env =3D &cpu->env;
=C2=A0 =C2=A0 =C2=A0hwaddr phys_addr;
=C2=A0 =C2=A0 =C2=A0target_ulong page_size;
=C2=A0 =C2=A0 =C2=A0int prot;
=C2=A0 =C2=A0 =C2=A0int ret;

-=C2=A0 =C2=A0 ret =3D get_phys_addr(&cpu->env, addr, 0, 0, &phy= s_addr, &prot, &page_size);
+=C2=A0 =C2=A0 ret =3D get_phys_addr(env, addr, 0, cpu_mmu_index(env), &= ;phys_addr,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 &prot, &page_size);

=C2=A0 =C2=A0 =C2=A0if (ret !=3D 0) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -1;
--
1.9.1



= =E2=80=8BOtherwise,

Reviewed-by: Greg Bellows <greg.bellows@linaro.org>=E2= =80=8B


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