From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:60450)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <greg.bellows@linaro.org>) id 1YEkei-0000mM-3d
	for qemu-devel@nongnu.org; Fri, 23 Jan 2015 15:16:40 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <greg.bellows@linaro.org>) id 1YEked-0002uq-17
	for qemu-devel@nongnu.org; Fri, 23 Jan 2015 15:16:36 -0500
Received: from mail-qg0-f46.google.com ([209.85.192.46]:42713)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <greg.bellows@linaro.org>) id 1YEkec-0002uc-Uj
	for qemu-devel@nongnu.org; Fri, 23 Jan 2015 15:16:30 -0500
Received: by mail-qg0-f46.google.com with SMTP id i50so7771754qgf.5
	for <qemu-devel@nongnu.org>; Fri, 23 Jan 2015 12:16:30 -0800 (PST)
MIME-Version: 1.0
In-Reply-To: <1422037228-5363-2-git-send-email-peter.maydell@linaro.org>
References: <1422037228-5363-1-git-send-email-peter.maydell@linaro.org>
	<1422037228-5363-2-git-send-email-peter.maydell@linaro.org>
Date: Fri, 23 Jan 2015 14:16:30 -0600
Message-ID: <CAOgzsHXr-i3FvPcSK1U7Ehs0j_E0_fvpz6yifnVLvOy9_1ZHbA@mail.gmail.com>
From: Greg Bellows <greg.bellows@linaro.org>
Content-Type: text/plain; charset=UTF-8
Subject: Re: [Qemu-devel] [PATCH 01/11] cpu_ldst.h: Allow NB_MMU_MODES to be
	7
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Andrew Jones <drjones@redhat.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, QEMU Developers <qemu-devel@nongnu.org>, Patch Tracking <patches@linaro.org>

On Fri, Jan 23, 2015 at 12:20 PM, Peter Maydell
<peter.maydell@linaro.org> wrote:
> Support guest CPUs which need 7 MMU index values.
> Add a comment about what would be required to raise the limit
> further (trivial for 8, TCG backend rework for 9 or more).
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  include/exec/cpu_ldst.h | 28 +++++++++++++++++++++++++---
>  1 file changed, 25 insertions(+), 3 deletions(-)
>
> diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
> index 0e825ea..fa5ea63 100644
> --- a/include/exec/cpu_ldst.h
> +++ b/include/exec/cpu_ldst.h
> @@ -244,9 +244,31 @@ uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
>  #undef MEMSUFFIX
>  #endif /* (NB_MMU_MODES >= 6) */
>
> -#if (NB_MMU_MODES > 6)
> -#error "NB_MMU_MODES > 6 is not supported for now"
> -#endif /* (NB_MMU_MODES > 6) */
> +#if (NB_MMU_MODES >= 7) && defined(MMU_MODE6_SUFFIX)
> +
> +#define CPU_MMU_INDEX 6
> +#define MEMSUFFIX MMU_MODE5_SUFFIX

Should this be MMU_MODE6_SUFFIX?

> +#define DATA_SIZE 1
> +#include "exec/cpu_ldst_template.h"
> +
> +#define DATA_SIZE 2
> +#include "exec/cpu_ldst_template.h"
> +
> +#define DATA_SIZE 4
> +#include "exec/cpu_ldst_template.h"
> +
> +#define DATA_SIZE 8
> +#include "exec/cpu_ldst_template.h"
> +#undef CPU_MMU_INDEX
> +#undef MEMSUFFIX
> +#endif /* (NB_MMU_MODES >= 7) */
> +
> +#if (NB_MMU_MODES > 7)
> +/* Note that supporting NB_MMU_MODES == 9 would require
> + * changes to at least the ARM TCG backend.
> + */
> +#error "NB_MMU_MODES > 7 is not supported for now"
> +#endif /* (NB_MMU_MODES > 7) */
>
>  /* these access are slower, they must be as rare as possible */
>  #define CPU_MMU_INDEX (cpu_mmu_index(env))
> --
> 1.9.1
>

Otherwise,
Reviewed-by: Greg Bellows <greg.bellows@linaro.org>