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Mon, 23 May 2022 07:41:45 -0700 (PDT) MIME-Version: 1.0 References: <20220522153543.2656-1-jszhang@kernel.org> <20220522153543.2656-3-jszhang@kernel.org> In-Reply-To: <20220522153543.2656-3-jszhang@kernel.org> From: Atish Patra Date: Mon, 23 May 2022 07:41:35 -0700 Message-ID: Subject: Re: [PATCH v2 2/2] riscv: switch has_fpu() to the unified static key mechanism To: Jisheng Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , linux-riscv , "linux-kernel@vger.kernel.org List" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, May 22, 2022 at 8:44 AM Jisheng Zhang wrote: > > This is to use the unified static key mechanism instead of putting > static key related here and there. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/include/asm/switch_to.h | 4 ++-- > arch/riscv/kernel/cpufeature.c | 7 ------- > 2 files changed, 2 insertions(+), 9 deletions(-) > > diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h > index 0a3f4f95c555..11463489fec6 100644 > --- a/arch/riscv/include/asm/switch_to.h > +++ b/arch/riscv/include/asm/switch_to.h > @@ -8,6 +8,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -56,10 +57,9 @@ static inline void __switch_to_aux(struct task_struct *prev, > fstate_restore(next, task_pt_regs(next)); > } > > -extern struct static_key_false cpu_hwcap_fpu; > static __always_inline bool has_fpu(void) > { > - return static_branch_likely(&cpu_hwcap_fpu); > + return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]); > } > #else > static __always_inline bool has_fpu(void) { return false; } > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 89f886b35357..0235391be84b 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -21,9 +21,6 @@ unsigned long elf_hwcap __read_mostly; > /* Host ISA bitmap */ > static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; > > -#ifdef CONFIG_FPU > -__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); > -#endif > __ro_after_init DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); > EXPORT_SYMBOL(riscv_isa_ext_keys); > > @@ -239,8 +236,4 @@ void __init riscv_fill_hwcap(void) > if (j >= 0) > static_branch_enable(&riscv_isa_ext_keys[j]); > } > -#ifdef CONFIG_FPU > - if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) > - static_branch_enable(&cpu_hwcap_fpu); > -#endif > } > -- > 2.34.1 > Reviewed-by: Atish Patra -- Regards, Atish From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 268C2C433F5 for ; Mon, 23 May 2022 14:42:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FIea/e0Gu5ysgbM0lza1MwLM3hy1nQONvtOxpkf/7bs=; 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Mon, 23 May 2022 07:41:45 -0700 (PDT) MIME-Version: 1.0 References: <20220522153543.2656-1-jszhang@kernel.org> <20220522153543.2656-3-jszhang@kernel.org> In-Reply-To: <20220522153543.2656-3-jszhang@kernel.org> From: Atish Patra Date: Mon, 23 May 2022 07:41:35 -0700 Message-ID: Subject: Re: [PATCH v2 2/2] riscv: switch has_fpu() to the unified static key mechanism To: Jisheng Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , linux-riscv , "linux-kernel@vger.kernel.org List" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220523_074147_997486_1F30648F X-CRM114-Status: GOOD ( 16.89 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, May 22, 2022 at 8:44 AM Jisheng Zhang wrote: > > This is to use the unified static key mechanism instead of putting > static key related here and there. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/include/asm/switch_to.h | 4 ++-- > arch/riscv/kernel/cpufeature.c | 7 ------- > 2 files changed, 2 insertions(+), 9 deletions(-) > > diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h > index 0a3f4f95c555..11463489fec6 100644 > --- a/arch/riscv/include/asm/switch_to.h > +++ b/arch/riscv/include/asm/switch_to.h > @@ -8,6 +8,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -56,10 +57,9 @@ static inline void __switch_to_aux(struct task_struct *prev, > fstate_restore(next, task_pt_regs(next)); > } > > -extern struct static_key_false cpu_hwcap_fpu; > static __always_inline bool has_fpu(void) > { > - return static_branch_likely(&cpu_hwcap_fpu); > + return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]); > } > #else > static __always_inline bool has_fpu(void) { return false; } > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 89f886b35357..0235391be84b 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -21,9 +21,6 @@ unsigned long elf_hwcap __read_mostly; > /* Host ISA bitmap */ > static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; > > -#ifdef CONFIG_FPU > -__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); > -#endif > __ro_after_init DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); > EXPORT_SYMBOL(riscv_isa_ext_keys); > > @@ -239,8 +236,4 @@ void __init riscv_fill_hwcap(void) > if (j >= 0) > static_branch_enable(&riscv_isa_ext_keys[j]); > } > -#ifdef CONFIG_FPU > - if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) > - static_branch_enable(&cpu_hwcap_fpu); > -#endif > } > -- > 2.34.1 > Reviewed-by: Atish Patra -- Regards, Atish _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv