* [PATCH v2 0/4] KVM RISC-V 64-bit selftests support
@ 2021-11-29 7:54 ` Anup Patel
0 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-11-29 7:54 UTC (permalink / raw)
To: Paolo Bonzini, Shuah Khan, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
linux-kselftest, Anup Patel
This series adds initial support for testing KVM RISC-V 64-bit using
kernel selftests framework. The PATCH1 & PATCH2 of this series does
some ground work in KVM RISC-V to implement RISC-V support in the KVM
selftests whereas remaining patches does required changes in the KVM
selftests.
These patches can be found in riscv_kvm_selftests_v2 branch at:
https://github.com/avpatel/linux.git
Changes since v1:
- Renamed kvm_sbi_ext_expevend_handler() to kvm_sbi_ext_forward_handler()
in PATCH1
- Renamed KVM_CAP_RISCV_VM_GPA_SIZE to KVM_CAP_VM_GPA_BITS in PATCH2
and PATCH4
Anup Patel (4):
RISC-V: KVM: Forward SBI experimental and vendor extensions
RISC-V: KVM: Add VM capability to allow userspace get GPA bits
KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
KVM: selftests: Add initial support for RISC-V 64-bit
arch/riscv/include/asm/kvm_host.h | 1 +
arch/riscv/kvm/mmu.c | 5 +
arch/riscv/kvm/vcpu_sbi.c | 4 +
arch/riscv/kvm/vcpu_sbi_base.c | 27 ++
arch/riscv/kvm/vm.c | 3 +
include/uapi/linux/kvm.h | 1 +
tools/testing/selftests/kvm/Makefile | 14 +-
.../testing/selftests/kvm/include/kvm_util.h | 10 +
.../selftests/kvm/include/riscv/processor.h | 135 +++++++
tools/testing/selftests/kvm/lib/guest_modes.c | 10 +
.../selftests/kvm/lib/riscv/processor.c | 362 ++++++++++++++++++
tools/testing/selftests/kvm/lib/riscv/ucall.c | 87 +++++
12 files changed, 658 insertions(+), 1 deletion(-)
create mode 100644 tools/testing/selftests/kvm/include/riscv/processor.h
create mode 100644 tools/testing/selftests/kvm/lib/riscv/processor.c
create mode 100644 tools/testing/selftests/kvm/lib/riscv/ucall.c
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v2 0/4] KVM RISC-V 64-bit selftests support
@ 2021-11-29 7:54 ` Anup Patel
0 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-11-29 7:54 UTC (permalink / raw)
To: Paolo Bonzini, Shuah Khan, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
linux-kselftest, Anup Patel
This series adds initial support for testing KVM RISC-V 64-bit using
kernel selftests framework. The PATCH1 & PATCH2 of this series does
some ground work in KVM RISC-V to implement RISC-V support in the KVM
selftests whereas remaining patches does required changes in the KVM
selftests.
These patches can be found in riscv_kvm_selftests_v2 branch at:
https://github.com/avpatel/linux.git
Changes since v1:
- Renamed kvm_sbi_ext_expevend_handler() to kvm_sbi_ext_forward_handler()
in PATCH1
- Renamed KVM_CAP_RISCV_VM_GPA_SIZE to KVM_CAP_VM_GPA_BITS in PATCH2
and PATCH4
Anup Patel (4):
RISC-V: KVM: Forward SBI experimental and vendor extensions
RISC-V: KVM: Add VM capability to allow userspace get GPA bits
KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
KVM: selftests: Add initial support for RISC-V 64-bit
arch/riscv/include/asm/kvm_host.h | 1 +
arch/riscv/kvm/mmu.c | 5 +
arch/riscv/kvm/vcpu_sbi.c | 4 +
arch/riscv/kvm/vcpu_sbi_base.c | 27 ++
arch/riscv/kvm/vm.c | 3 +
include/uapi/linux/kvm.h | 1 +
tools/testing/selftests/kvm/Makefile | 14 +-
.../testing/selftests/kvm/include/kvm_util.h | 10 +
.../selftests/kvm/include/riscv/processor.h | 135 +++++++
tools/testing/selftests/kvm/lib/guest_modes.c | 10 +
.../selftests/kvm/lib/riscv/processor.c | 362 ++++++++++++++++++
tools/testing/selftests/kvm/lib/riscv/ucall.c | 87 +++++
12 files changed, 658 insertions(+), 1 deletion(-)
create mode 100644 tools/testing/selftests/kvm/include/riscv/processor.h
create mode 100644 tools/testing/selftests/kvm/lib/riscv/processor.c
create mode 100644 tools/testing/selftests/kvm/lib/riscv/ucall.c
--
2.25.1
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v2 1/4] RISC-V: KVM: Forward SBI experimental and vendor extensions
2021-11-29 7:54 ` Anup Patel
@ 2021-11-29 7:54 ` Anup Patel
-1 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-11-29 7:54 UTC (permalink / raw)
To: Paolo Bonzini, Shuah Khan, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
linux-kselftest, Anup Patel
The SBI experimental extension space is for temporary (or experimental)
stuff whereas SBI vendor extension space is for hardware vendor specific
stuff. Both these SBI extension spaces won't be standardized by the SBI
specification so let's blindly forward such SBI calls to the userspace.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/kvm/vcpu_sbi.c | 4 ++++
arch/riscv/kvm/vcpu_sbi_base.c | 27 +++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
index f62d25bc9733..78aa3db76225 100644
--- a/arch/riscv/kvm/vcpu_sbi.c
+++ b/arch/riscv/kvm/vcpu_sbi.c
@@ -46,6 +46,8 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time;
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi;
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence;
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm;
+extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental;
+extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor;
static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
&vcpu_sbi_ext_v01,
@@ -54,6 +56,8 @@ static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
&vcpu_sbi_ext_ipi,
&vcpu_sbi_ext_rfence,
&vcpu_sbi_ext_hsm,
+ &vcpu_sbi_ext_experimental,
+ &vcpu_sbi_ext_vendor,
};
void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run)
diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 641015549d12..ac0537d479d8 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -68,3 +68,30 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_base = {
.extid_end = SBI_EXT_BASE,
.handler = kvm_sbi_ext_base_handler,
};
+
+static int kvm_sbi_ext_forward_handler(struct kvm_vcpu *vcpu,
+ struct kvm_run *run,
+ unsigned long *out_val,
+ struct kvm_cpu_trap *utrap,
+ bool *exit)
+{
+ /*
+ * Both SBI experimental and vendor extensions are
+ * unconditionally forwarded to userspace.
+ */
+ kvm_riscv_vcpu_sbi_forward(vcpu, run);
+ *exit = true;
+ return 0;
+}
+
+const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental = {
+ .extid_start = SBI_EXT_EXPERIMENTAL_START,
+ .extid_end = SBI_EXT_EXPERIMENTAL_END,
+ .handler = kvm_sbi_ext_forward_handler,
+};
+
+const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor = {
+ .extid_start = SBI_EXT_VENDOR_START,
+ .extid_end = SBI_EXT_VENDOR_END,
+ .handler = kvm_sbi_ext_forward_handler,
+};
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 1/4] RISC-V: KVM: Forward SBI experimental and vendor extensions
@ 2021-11-29 7:54 ` Anup Patel
0 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-11-29 7:54 UTC (permalink / raw)
To: Paolo Bonzini, Shuah Khan, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
linux-kselftest, Anup Patel
The SBI experimental extension space is for temporary (or experimental)
stuff whereas SBI vendor extension space is for hardware vendor specific
stuff. Both these SBI extension spaces won't be standardized by the SBI
specification so let's blindly forward such SBI calls to the userspace.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/kvm/vcpu_sbi.c | 4 ++++
arch/riscv/kvm/vcpu_sbi_base.c | 27 +++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
index f62d25bc9733..78aa3db76225 100644
--- a/arch/riscv/kvm/vcpu_sbi.c
+++ b/arch/riscv/kvm/vcpu_sbi.c
@@ -46,6 +46,8 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time;
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi;
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence;
extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm;
+extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental;
+extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor;
static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
&vcpu_sbi_ext_v01,
@@ -54,6 +56,8 @@ static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
&vcpu_sbi_ext_ipi,
&vcpu_sbi_ext_rfence,
&vcpu_sbi_ext_hsm,
+ &vcpu_sbi_ext_experimental,
+ &vcpu_sbi_ext_vendor,
};
void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run)
diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
index 641015549d12..ac0537d479d8 100644
--- a/arch/riscv/kvm/vcpu_sbi_base.c
+++ b/arch/riscv/kvm/vcpu_sbi_base.c
@@ -68,3 +68,30 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_base = {
.extid_end = SBI_EXT_BASE,
.handler = kvm_sbi_ext_base_handler,
};
+
+static int kvm_sbi_ext_forward_handler(struct kvm_vcpu *vcpu,
+ struct kvm_run *run,
+ unsigned long *out_val,
+ struct kvm_cpu_trap *utrap,
+ bool *exit)
+{
+ /*
+ * Both SBI experimental and vendor extensions are
+ * unconditionally forwarded to userspace.
+ */
+ kvm_riscv_vcpu_sbi_forward(vcpu, run);
+ *exit = true;
+ return 0;
+}
+
+const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental = {
+ .extid_start = SBI_EXT_EXPERIMENTAL_START,
+ .extid_end = SBI_EXT_EXPERIMENTAL_END,
+ .handler = kvm_sbi_ext_forward_handler,
+};
+
+const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor = {
+ .extid_start = SBI_EXT_VENDOR_START,
+ .extid_end = SBI_EXT_VENDOR_END,
+ .handler = kvm_sbi_ext_forward_handler,
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA bits
2021-11-29 7:54 ` Anup Patel
@ 2021-11-29 7:54 ` Anup Patel
-1 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-11-29 7:54 UTC (permalink / raw)
To: Paolo Bonzini, Shuah Khan, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
linux-kselftest, Anup Patel
The number of GPA bits supported for a RISC-V Guest/VM is based on the
MMU mode used by the G-stage translation. The KVM RISC-V will detect and
use the best possible MMU mode for the G-stage in kvm_arch_init().
We add a generic VM capability KVM_CAP_VM_GPA_BITS which can be used by
the KVM userspace to get the number of GPA (guest physical address) bits
supported for a Guest/VM.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/include/asm/kvm_host.h | 1 +
arch/riscv/kvm/mmu.c | 5 +++++
arch/riscv/kvm/vm.c | 3 +++
include/uapi/linux/kvm.h | 1 +
4 files changed, 10 insertions(+)
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 37589b953bcb..ae5d238607fe 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -221,6 +221,7 @@ void kvm_riscv_stage2_free_pgd(struct kvm *kvm);
void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu);
void kvm_riscv_stage2_mode_detect(void);
unsigned long kvm_riscv_stage2_mode(void);
+int kvm_riscv_stage2_gpa_size(void);
void kvm_riscv_stage2_vmid_detect(void);
unsigned long kvm_riscv_stage2_vmid_bits(void);
diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
index 9ffd0255af43..9b6d6465094f 100644
--- a/arch/riscv/kvm/mmu.c
+++ b/arch/riscv/kvm/mmu.c
@@ -760,3 +760,8 @@ unsigned long kvm_riscv_stage2_mode(void)
{
return stage2_mode >> HGATP_MODE_SHIFT;
}
+
+int kvm_riscv_stage2_gpa_size(void)
+{
+ return stage2_gpa_bits;
+}
diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c
index fb18af34a4b5..6f959639ec45 100644
--- a/arch/riscv/kvm/vm.c
+++ b/arch/riscv/kvm/vm.c
@@ -82,6 +82,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
case KVM_CAP_NR_MEMSLOTS:
r = KVM_USER_MEM_SLOTS;
break;
+ case KVM_CAP_VM_GPA_BITS:
+ r = kvm_riscv_stage2_gpa_size();
+ break;
default:
r = 0;
break;
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 1daa45268de2..469f05d69c8d 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1131,6 +1131,7 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204
#define KVM_CAP_ARM_MTE 205
#define KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM 206
+#define KVM_CAP_VM_GPA_BITS 207
#ifdef KVM_CAP_IRQ_ROUTING
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA bits
@ 2021-11-29 7:54 ` Anup Patel
0 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-11-29 7:54 UTC (permalink / raw)
To: Paolo Bonzini, Shuah Khan, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
linux-kselftest, Anup Patel
The number of GPA bits supported for a RISC-V Guest/VM is based on the
MMU mode used by the G-stage translation. The KVM RISC-V will detect and
use the best possible MMU mode for the G-stage in kvm_arch_init().
We add a generic VM capability KVM_CAP_VM_GPA_BITS which can be used by
the KVM userspace to get the number of GPA (guest physical address) bits
supported for a Guest/VM.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
arch/riscv/include/asm/kvm_host.h | 1 +
arch/riscv/kvm/mmu.c | 5 +++++
arch/riscv/kvm/vm.c | 3 +++
include/uapi/linux/kvm.h | 1 +
4 files changed, 10 insertions(+)
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 37589b953bcb..ae5d238607fe 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -221,6 +221,7 @@ void kvm_riscv_stage2_free_pgd(struct kvm *kvm);
void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu);
void kvm_riscv_stage2_mode_detect(void);
unsigned long kvm_riscv_stage2_mode(void);
+int kvm_riscv_stage2_gpa_size(void);
void kvm_riscv_stage2_vmid_detect(void);
unsigned long kvm_riscv_stage2_vmid_bits(void);
diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
index 9ffd0255af43..9b6d6465094f 100644
--- a/arch/riscv/kvm/mmu.c
+++ b/arch/riscv/kvm/mmu.c
@@ -760,3 +760,8 @@ unsigned long kvm_riscv_stage2_mode(void)
{
return stage2_mode >> HGATP_MODE_SHIFT;
}
+
+int kvm_riscv_stage2_gpa_size(void)
+{
+ return stage2_gpa_bits;
+}
diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c
index fb18af34a4b5..6f959639ec45 100644
--- a/arch/riscv/kvm/vm.c
+++ b/arch/riscv/kvm/vm.c
@@ -82,6 +82,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
case KVM_CAP_NR_MEMSLOTS:
r = KVM_USER_MEM_SLOTS;
break;
+ case KVM_CAP_VM_GPA_BITS:
+ r = kvm_riscv_stage2_gpa_size();
+ break;
default:
r = 0;
break;
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 1daa45268de2..469f05d69c8d 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1131,6 +1131,7 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204
#define KVM_CAP_ARM_MTE 205
#define KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM 206
+#define KVM_CAP_VM_GPA_BITS 207
#ifdef KVM_CAP_IRQ_ROUTING
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 3/4] KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
2021-11-29 7:54 ` Anup Patel
@ 2021-11-29 7:54 ` Anup Patel
-1 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-11-29 7:54 UTC (permalink / raw)
To: Paolo Bonzini, Shuah Khan, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
linux-kselftest, Anup Patel
We add EXTRA_CFLAGS to the common CFLAGS of top-level Makefile
which will allow users to pass additional compile-time flags such
as "-static".
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
tools/testing/selftests/kvm/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index c4e34717826a..ee6740e9ecdb 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -131,7 +131,7 @@ endif
CFLAGS += -Wall -Wstrict-prototypes -Wuninitialized -O2 -g -std=gnu99 \
-fno-stack-protector -fno-PIE -I$(LINUX_TOOL_INCLUDE) \
-I$(LINUX_TOOL_ARCH_INCLUDE) -I$(LINUX_HDR_PATH) -Iinclude \
- -I$(<D) -Iinclude/$(UNAME_M) -I..
+ -I$(<D) -Iinclude/$(UNAME_M) -I.. $(EXTRA_CFLAGS)
no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
$(CC) -Werror -no-pie -x c - -o "$$TMP", -no-pie)
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 3/4] KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
@ 2021-11-29 7:54 ` Anup Patel
0 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-11-29 7:54 UTC (permalink / raw)
To: Paolo Bonzini, Shuah Khan, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
linux-kselftest, Anup Patel
We add EXTRA_CFLAGS to the common CFLAGS of top-level Makefile
which will allow users to pass additional compile-time flags such
as "-static".
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
tools/testing/selftests/kvm/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index c4e34717826a..ee6740e9ecdb 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -131,7 +131,7 @@ endif
CFLAGS += -Wall -Wstrict-prototypes -Wuninitialized -O2 -g -std=gnu99 \
-fno-stack-protector -fno-PIE -I$(LINUX_TOOL_INCLUDE) \
-I$(LINUX_TOOL_ARCH_INCLUDE) -I$(LINUX_HDR_PATH) -Iinclude \
- -I$(<D) -Iinclude/$(UNAME_M) -I..
+ -I$(<D) -Iinclude/$(UNAME_M) -I.. $(EXTRA_CFLAGS)
no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
$(CC) -Werror -no-pie -x c - -o "$$TMP", -no-pie)
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 4/4] KVM: selftests: Add initial support for RISC-V 64-bit
2021-11-29 7:54 ` Anup Patel
@ 2021-11-29 7:54 ` Anup Patel
-1 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-11-29 7:54 UTC (permalink / raw)
To: Paolo Bonzini, Shuah Khan, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
linux-kselftest, Anup Patel
We add initial support for RISC-V 64-bit in KVM selftests using
which we can cross-compile and run arch independent tests such as:
demand_paging_test
dirty_log_test
kvm_create_max_vcpus,
kvm_page_table_test
set_memory_region_test
kvm_binary_stats_test
All VM guest modes defined in kvm_util.h require at least 48-bit
guest virtual address so to use KVM RISC-V selftests hardware
need to support at least Sv48 MMU for guest (i.e. VS-mode).
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
tools/testing/selftests/kvm/Makefile | 12 +
.../testing/selftests/kvm/include/kvm_util.h | 10 +
.../selftests/kvm/include/riscv/processor.h | 135 +++++++
tools/testing/selftests/kvm/lib/guest_modes.c | 10 +
.../selftests/kvm/lib/riscv/processor.c | 362 ++++++++++++++++++
tools/testing/selftests/kvm/lib/riscv/ucall.c | 87 +++++
6 files changed, 616 insertions(+)
create mode 100644 tools/testing/selftests/kvm/include/riscv/processor.h
create mode 100644 tools/testing/selftests/kvm/lib/riscv/processor.c
create mode 100644 tools/testing/selftests/kvm/lib/riscv/ucall.c
diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index ee6740e9ecdb..2d825d1e7ff2 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -32,11 +32,16 @@ endif
ifeq ($(ARCH),s390)
UNAME_M := s390x
endif
+# Set UNAME_M riscv compile/install to work
+ifeq ($(ARCH),riscv)
+ UNAME_M := riscv
+endif
LIBKVM = lib/assert.c lib/elf.c lib/io.c lib/kvm_util.c lib/rbtree.c lib/sparsebit.c lib/test_util.c lib/guest_modes.c lib/perf_test_util.c
LIBKVM_x86_64 = lib/x86_64/apic.c lib/x86_64/processor.c lib/x86_64/vmx.c lib/x86_64/svm.c lib/x86_64/ucall.c lib/x86_64/handlers.S
LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S lib/aarch64/spinlock.c lib/aarch64/gic.c lib/aarch64/gic_v3.c lib/aarch64/vgic.c
LIBKVM_s390x = lib/s390x/processor.c lib/s390x/ucall.c lib/s390x/diag318_test_handler.c
+LIBKVM_riscv = lib/riscv/processor.c lib/riscv/ucall.c
TEST_GEN_PROGS_x86_64 = x86_64/cr4_cpuid_sync_test
TEST_GEN_PROGS_x86_64 += x86_64/get_msr_index_features
@@ -117,6 +122,13 @@ TEST_GEN_PROGS_s390x += rseq_test
TEST_GEN_PROGS_s390x += set_memory_region_test
TEST_GEN_PROGS_s390x += kvm_binary_stats_test
+TEST_GEN_PROGS_riscv += demand_paging_test
+TEST_GEN_PROGS_riscv += dirty_log_test
+TEST_GEN_PROGS_riscv += kvm_create_max_vcpus
+TEST_GEN_PROGS_riscv += kvm_page_table_test
+TEST_GEN_PROGS_riscv += set_memory_region_test
+TEST_GEN_PROGS_riscv += kvm_binary_stats_test
+
TEST_GEN_PROGS += $(TEST_GEN_PROGS_$(UNAME_M))
LIBKVM += $(LIBKVM_$(UNAME_M))
diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h
index 6a1a37f30494..c23e5be14862 100644
--- a/tools/testing/selftests/kvm/include/kvm_util.h
+++ b/tools/testing/selftests/kvm/include/kvm_util.h
@@ -69,6 +69,16 @@ enum vm_guest_mode {
#define MIN_PAGE_SHIFT 12U
#define ptes_per_page(page_size) ((page_size) / 16)
+#elif defined(__riscv)
+
+#if __riscv_xlen == 32
+#error "RISC-V 32-bit kvm selftests not supported"
+#endif
+
+#define VM_MODE_DEFAULT VM_MODE_P40V48_4K
+#define MIN_PAGE_SHIFT 12U
+#define ptes_per_page(page_size) ((page_size) / 8)
+
#endif
#define MIN_PAGE_SIZE (1U << MIN_PAGE_SHIFT)
diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
new file mode 100644
index 000000000000..dc284c6bdbc3
--- /dev/null
+++ b/tools/testing/selftests/kvm/include/riscv/processor.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * RISC-V processor specific defines
+ *
+ * Copyright (C) 2021 Western Digital Corporation or its affiliates.
+ */
+#ifndef SELFTEST_KVM_PROCESSOR_H
+#define SELFTEST_KVM_PROCESSOR_H
+
+#include "kvm_util.h"
+#include <linux/stringify.h>
+
+static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx,
+ uint64_t size)
+{
+ return KVM_REG_RISCV | type | idx | size;
+}
+
+#if __riscv_xlen == 64
+#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64
+#else
+#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32
+#endif
+
+#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, \
+ KVM_REG_RISCV_CONFIG_REG(name), \
+ KVM_REG_SIZE_ULONG)
+
+#define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, \
+ KVM_REG_RISCV_CORE_REG(name), \
+ KVM_REG_SIZE_ULONG)
+
+#define RISCV_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \
+ KVM_REG_RISCV_CSR_REG(name), \
+ KVM_REG_SIZE_ULONG)
+
+#define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, \
+ KVM_REG_RISCV_TIMER_REG(name), \
+ KVM_REG_SIZE_U64)
+
+static inline void get_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
+ unsigned long *addr)
+{
+ struct kvm_one_reg reg;
+
+ reg.id = id;
+ reg.addr = (unsigned long)addr;
+ vcpu_get_reg(vm, vcpuid, ®);
+}
+
+static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
+ unsigned long val)
+{
+ struct kvm_one_reg reg;
+
+ reg.id = id;
+ reg.addr = (unsigned long)&val;
+ vcpu_set_reg(vm, vcpuid, ®);
+}
+
+/* L3 index Bit[47:39] */
+#define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL
+#define PGTBL_L3_INDEX_SHIFT 39
+#define PGTBL_L3_BLOCK_SHIFT 39
+#define PGTBL_L3_BLOCK_SIZE 0x0000008000000000ULL
+#define PGTBL_L3_MAP_MASK (~(PGTBL_L3_BLOCK_SIZE - 1))
+/* L2 index Bit[38:30] */
+#define PGTBL_L2_INDEX_MASK 0x0000007FC0000000ULL
+#define PGTBL_L2_INDEX_SHIFT 30
+#define PGTBL_L2_BLOCK_SHIFT 30
+#define PGTBL_L2_BLOCK_SIZE 0x0000000040000000ULL
+#define PGTBL_L2_MAP_MASK (~(PGTBL_L2_BLOCK_SIZE - 1))
+/* L1 index Bit[29:21] */
+#define PGTBL_L1_INDEX_MASK 0x000000003FE00000ULL
+#define PGTBL_L1_INDEX_SHIFT 21
+#define PGTBL_L1_BLOCK_SHIFT 21
+#define PGTBL_L1_BLOCK_SIZE 0x0000000000200000ULL
+#define PGTBL_L1_MAP_MASK (~(PGTBL_L1_BLOCK_SIZE - 1))
+/* L0 index Bit[20:12] */
+#define PGTBL_L0_INDEX_MASK 0x00000000001FF000ULL
+#define PGTBL_L0_INDEX_SHIFT 12
+#define PGTBL_L0_BLOCK_SHIFT 12
+#define PGTBL_L0_BLOCK_SIZE 0x0000000000001000ULL
+#define PGTBL_L0_MAP_MASK (~(PGTBL_L0_BLOCK_SIZE - 1))
+
+#define PGTBL_PTE_ADDR_MASK 0x003FFFFFFFFFFC00ULL
+#define PGTBL_PTE_ADDR_SHIFT 10
+#define PGTBL_PTE_RSW_MASK 0x0000000000000300ULL
+#define PGTBL_PTE_RSW_SHIFT 8
+#define PGTBL_PTE_DIRTY_MASK 0x0000000000000080ULL
+#define PGTBL_PTE_DIRTY_SHIFT 7
+#define PGTBL_PTE_ACCESSED_MASK 0x0000000000000040ULL
+#define PGTBL_PTE_ACCESSED_SHIFT 6
+#define PGTBL_PTE_GLOBAL_MASK 0x0000000000000020ULL
+#define PGTBL_PTE_GLOBAL_SHIFT 5
+#define PGTBL_PTE_USER_MASK 0x0000000000000010ULL
+#define PGTBL_PTE_USER_SHIFT 4
+#define PGTBL_PTE_EXECUTE_MASK 0x0000000000000008ULL
+#define PGTBL_PTE_EXECUTE_SHIFT 3
+#define PGTBL_PTE_WRITE_MASK 0x0000000000000004ULL
+#define PGTBL_PTE_WRITE_SHIFT 2
+#define PGTBL_PTE_READ_MASK 0x0000000000000002ULL
+#define PGTBL_PTE_READ_SHIFT 1
+#define PGTBL_PTE_PERM_MASK (PGTBL_PTE_EXECUTE_MASK | \
+ PGTBL_PTE_WRITE_MASK | \
+ PGTBL_PTE_READ_MASK)
+#define PGTBL_PTE_VALID_MASK 0x0000000000000001ULL
+#define PGTBL_PTE_VALID_SHIFT 0
+
+#define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE
+#define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT
+
+#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
+#define SATP_MODE_39 _AC(0x8000000000000000, UL)
+#define SATP_MODE_48 _AC(0x9000000000000000, UL)
+#define SATP_ASID_BITS 16
+#define SATP_ASID_SHIFT 44
+#define SATP_ASID_MASK _AC(0xFFFF, UL)
+
+#define SBI_EXT_EXPERIMENTAL_START 0x08000000
+#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF
+
+#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END
+
+struct sbiret {
+ long error;
+ long value;
+};
+
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5);
+
+#endif /* SELFTEST_KVM_PROCESSOR_H */
diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/selftests/kvm/lib/guest_modes.c
index c330f414ef96..57839a12e472 100644
--- a/tools/testing/selftests/kvm/lib/guest_modes.c
+++ b/tools/testing/selftests/kvm/lib/guest_modes.c
@@ -38,6 +38,16 @@ void guest_modes_append_default(void)
guest_mode_append(VM_MODE_P47V64_4K, true, true);
}
#endif
+#ifdef __riscv
+ {
+ unsigned int sz = kvm_check_cap(KVM_CAP_VM_GPA_BITS);
+
+ if (sz >= 52)
+ guest_mode_append(VM_MODE_P52V48_4K, true, true);
+ if (sz >= 48)
+ guest_mode_append(VM_MODE_P48V48_4K, true, true);
+ }
+#endif
}
void for_each_guest_mode(void (*func)(enum vm_guest_mode, void *), void *arg)
diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
new file mode 100644
index 000000000000..d377f2603d98
--- /dev/null
+++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RISC-V code
+ *
+ * Copyright (C) 2021 Western Digital Corporation or its affiliates.
+ */
+
+#include <linux/compiler.h>
+#include <assert.h>
+
+#include "kvm_util.h"
+#include "../kvm_util_internal.h"
+#include "processor.h"
+
+#define DEFAULT_RISCV_GUEST_STACK_VADDR_MIN 0xac0000
+
+static uint64_t page_align(struct kvm_vm *vm, uint64_t v)
+{
+ return (v + vm->page_size) & ~(vm->page_size - 1);
+}
+
+static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry)
+{
+ return ((entry & PGTBL_PTE_ADDR_MASK) >> PGTBL_PTE_ADDR_SHIFT) <<
+ PGTBL_PAGE_SIZE_SHIFT;
+}
+
+static uint64_t ptrs_per_pte(struct kvm_vm *vm)
+{
+ return PGTBL_PAGE_SIZE / sizeof(uint64_t);
+}
+
+static uint64_t pte_index_mask[] = {
+ PGTBL_L0_INDEX_MASK,
+ PGTBL_L1_INDEX_MASK,
+ PGTBL_L2_INDEX_MASK,
+ PGTBL_L3_INDEX_MASK,
+};
+
+static uint32_t pte_index_shift[] = {
+ PGTBL_L0_INDEX_SHIFT,
+ PGTBL_L1_INDEX_SHIFT,
+ PGTBL_L2_INDEX_SHIFT,
+ PGTBL_L3_INDEX_SHIFT,
+};
+
+static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level)
+{
+ TEST_ASSERT(level > -1,
+ "Negative page table level (%d) not possible", level);
+ TEST_ASSERT(level < vm->pgtable_levels,
+ "Invalid page table level (%d)", level);
+
+ return (gva & pte_index_mask[level]) >> pte_index_shift[level];
+}
+
+void virt_pgd_alloc(struct kvm_vm *vm)
+{
+ if (!vm->pgd_created) {
+ vm_paddr_t paddr = vm_phy_pages_alloc(vm,
+ page_align(vm, ptrs_per_pte(vm) * 8) / vm->page_size,
+ KVM_GUEST_PAGE_TABLE_MIN_PADDR, 0);
+ vm->pgd = paddr;
+ vm->pgd_created = true;
+ }
+}
+
+void virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
+{
+ uint64_t *ptep, next_ppn;
+ int level = vm->pgtable_levels - 1;
+
+ TEST_ASSERT((vaddr % vm->page_size) == 0,
+ "Virtual address not on page boundary,\n"
+ " vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size);
+ TEST_ASSERT(sparsebit_is_set(vm->vpages_valid,
+ (vaddr >> vm->page_shift)),
+ "Invalid virtual address, vaddr: 0x%lx", vaddr);
+ TEST_ASSERT((paddr % vm->page_size) == 0,
+ "Physical address not on page boundary,\n"
+ " paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size);
+ TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
+ "Physical address beyond maximum supported,\n"
+ " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
+ paddr, vm->max_gfn, vm->page_size);
+
+ ptep = addr_gpa2hva(vm, vm->pgd) + pte_index(vm, vaddr, level) * 8;
+ if (!*ptep) {
+ next_ppn = vm_alloc_page_table(vm) >> PGTBL_PAGE_SIZE_SHIFT;
+ *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) |
+ PGTBL_PTE_VALID_MASK;
+ }
+ level--;
+
+ while (level > -1) {
+ ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) +
+ pte_index(vm, vaddr, level) * 8;
+ if (!*ptep && level > 0) {
+ next_ppn = vm_alloc_page_table(vm) >>
+ PGTBL_PAGE_SIZE_SHIFT;
+ *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) |
+ PGTBL_PTE_VALID_MASK;
+ }
+ level--;
+ }
+
+ paddr = paddr >> PGTBL_PAGE_SIZE_SHIFT;
+ *ptep = (paddr << PGTBL_PTE_ADDR_SHIFT) |
+ PGTBL_PTE_PERM_MASK | PGTBL_PTE_VALID_MASK;
+}
+
+vm_paddr_t addr_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
+{
+ uint64_t *ptep;
+ int level = vm->pgtable_levels - 1;
+
+ if (!vm->pgd_created)
+ goto unmapped_gva;
+
+ ptep = addr_gpa2hva(vm, vm->pgd) + pte_index(vm, gva, level) * 8;
+ if (!ptep)
+ goto unmapped_gva;
+ level--;
+
+ while (level > -1) {
+ ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) +
+ pte_index(vm, gva, level) * 8;
+ if (!ptep)
+ goto unmapped_gva;
+ level--;
+ }
+
+ return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1));
+
+unmapped_gva:
+ TEST_FAIL("No mapping for vm virtual address gva: 0x%lx level: %d",
+ gva, level);
+ exit(1);
+}
+
+static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent,
+ uint64_t page, int level)
+{
+#ifdef DEBUG
+ static const char *const type[] = { "pte", "pmd", "pud", "p4d"};
+ uint64_t pte, *ptep;
+
+ if (level < 0)
+ return;
+
+ for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) {
+ ptep = addr_gpa2hva(vm, pte);
+ if (!*ptep)
+ continue;
+ fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "",
+ type[level], pte, *ptep, ptep);
+ pte_dump(stream, vm, indent + 1,
+ pte_addr(vm, *ptep), level - 1);
+ }
+#endif
+}
+
+void virt_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
+{
+ int level = vm->pgtable_levels - 1;
+ uint64_t pgd, *ptep;
+
+ if (!vm->pgd_created)
+ return;
+
+ for (pgd = vm->pgd; pgd < vm->pgd + ptrs_per_pte(vm) * 8; pgd += 8) {
+ ptep = addr_gpa2hva(vm, pgd);
+ if (!*ptep)
+ continue;
+ fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "",
+ pgd, *ptep, ptep);
+ pte_dump(stream, vm, indent + 1,
+ pte_addr(vm, *ptep), level - 1);
+ }
+}
+
+void riscv_vcpu_mmu_setup(struct kvm_vm *vm, int vcpuid)
+{
+ unsigned long satp;
+
+ /*
+ * The RISC-V Sv48 MMU mode supports 56-bit physical address
+ * for 48-bit virtual address with 4KB last level page size.
+ */
+ switch (vm->mode) {
+ case VM_MODE_P52V48_4K:
+ case VM_MODE_P48V48_4K:
+ case VM_MODE_P40V48_4K:
+ break;
+ default:
+ TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode);
+ }
+
+ satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN;
+ satp |= SATP_MODE_48;
+
+ set_reg(vm, vcpuid, RISCV_CSR_REG(satp), satp);
+}
+
+void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint8_t indent)
+{
+ struct kvm_riscv_core core;
+
+ get_reg(vm, vcpuid, RISCV_CORE_REG(mode), &core.mode);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.pc), &core.regs.pc);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.ra), &core.regs.ra);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.sp), &core.regs.sp);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.gp), &core.regs.gp);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.tp), &core.regs.tp);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t0), &core.regs.t0);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t1), &core.regs.t1);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t2), &core.regs.t2);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s0), &core.regs.s0);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s1), &core.regs.s1);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a0), &core.regs.a0);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a1), &core.regs.a1);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a2), &core.regs.a2);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a3), &core.regs.a3);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a4), &core.regs.a4);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a5), &core.regs.a5);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a6), &core.regs.a6);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a7), &core.regs.a7);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s2), &core.regs.s2);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s3), &core.regs.s3);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s4), &core.regs.s4);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s5), &core.regs.s5);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s6), &core.regs.s6);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s7), &core.regs.s7);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s8), &core.regs.s8);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s9), &core.regs.s9);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s10), &core.regs.s10);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s11), &core.regs.s11);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t3), &core.regs.t3);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t4), &core.regs.t4);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t5), &core.regs.t5);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t6), &core.regs.t6);
+
+ fprintf(stream,
+ " MODE: 0x%lx\n", core.mode);
+ fprintf(stream,
+ " PC: 0x%016lx RA: 0x%016lx SP: 0x%016lx GP: 0x%016lx\n",
+ core.regs.pc, core.regs.ra, core.regs.sp, core.regs.gp);
+ fprintf(stream,
+ " TP: 0x%016lx T0: 0x%016lx T1: 0x%016lx T2: 0x%016lx\n",
+ core.regs.tp, core.regs.t0, core.regs.t1, core.regs.t2);
+ fprintf(stream,
+ " S0: 0x%016lx S1: 0x%016lx A0: 0x%016lx A1: 0x%016lx\n",
+ core.regs.s0, core.regs.s1, core.regs.a0, core.regs.a1);
+ fprintf(stream,
+ " A2: 0x%016lx A3: 0x%016lx A4: 0x%016lx A5: 0x%016lx\n",
+ core.regs.a2, core.regs.a3, core.regs.a4, core.regs.a5);
+ fprintf(stream,
+ " A6: 0x%016lx A7: 0x%016lx S2: 0x%016lx S3: 0x%016lx\n",
+ core.regs.a6, core.regs.a7, core.regs.s2, core.regs.s3);
+ fprintf(stream,
+ " S4: 0x%016lx S5: 0x%016lx S6: 0x%016lx S7: 0x%016lx\n",
+ core.regs.s4, core.regs.s5, core.regs.s6, core.regs.s7);
+ fprintf(stream,
+ " S8: 0x%016lx S9: 0x%016lx S10: 0x%016lx S11: 0x%016lx\n",
+ core.regs.s8, core.regs.s9, core.regs.s10, core.regs.s11);
+ fprintf(stream,
+ " T3: 0x%016lx T4: 0x%016lx T5: 0x%016lx T6: 0x%016lx\n",
+ core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6);
+}
+
+static void guest_hang(void)
+{
+ while (1)
+ ;
+}
+
+void vm_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, void *guest_code)
+{
+ int r;
+ size_t stack_size = vm->page_size == 4096 ?
+ DEFAULT_STACK_PGS * vm->page_size :
+ vm->page_size;
+ unsigned long stack_vaddr = vm_vaddr_alloc(vm, stack_size,
+ DEFAULT_RISCV_GUEST_STACK_VADDR_MIN);
+ unsigned long current_gp = 0;
+ struct kvm_mp_state mps;
+
+ vm_vcpu_add(vm, vcpuid);
+ riscv_vcpu_mmu_setup(vm, vcpuid);
+
+ /*
+ * With SBI HSM support in KVM RISC-V, all secondary VCPUs are
+ * powered-off by default so we ensure that all secondary VCPUs
+ * are powered-on using KVM_SET_MP_STATE ioctl().
+ */
+ mps.mp_state = KVM_MP_STATE_RUNNABLE;
+ r = _vcpu_ioctl(vm, vcpuid, KVM_SET_MP_STATE, &mps);
+ TEST_ASSERT(!r, "IOCTL KVM_SET_MP_STATE failed (error %d)", r);
+
+ /* Setup global pointer of guest to be same as the host */
+ asm volatile (
+ "add %0, gp, zero" : "=r" (current_gp) : : "memory");
+ set_reg(vm, vcpuid, RISCV_CORE_REG(regs.gp), current_gp);
+
+ /* Setup stack pointer and program counter of guest */
+ set_reg(vm, vcpuid, RISCV_CORE_REG(regs.sp),
+ stack_vaddr + stack_size);
+ set_reg(vm, vcpuid, RISCV_CORE_REG(regs.pc),
+ (unsigned long)guest_code);
+
+ /* Setup default exception vector of guest */
+ set_reg(vm, vcpuid, RISCV_CSR_REG(stvec),
+ (unsigned long)guest_hang);
+}
+
+void vcpu_args_set(struct kvm_vm *vm, uint32_t vcpuid, unsigned int num, ...)
+{
+ va_list ap;
+ uint64_t id = RISCV_CORE_REG(regs.a0);
+ int i;
+
+ TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n"
+ " num: %u\n", num);
+
+ va_start(ap, num);
+
+ for (i = 0; i < num; i++) {
+ switch (i) {
+ case 0:
+ id = RISCV_CORE_REG(regs.a0);
+ break;
+ case 1:
+ id = RISCV_CORE_REG(regs.a1);
+ break;
+ case 2:
+ id = RISCV_CORE_REG(regs.a2);
+ break;
+ case 3:
+ id = RISCV_CORE_REG(regs.a3);
+ break;
+ case 4:
+ id = RISCV_CORE_REG(regs.a4);
+ break;
+ case 5:
+ id = RISCV_CORE_REG(regs.a5);
+ break;
+ case 6:
+ id = RISCV_CORE_REG(regs.a6);
+ break;
+ case 7:
+ id = RISCV_CORE_REG(regs.a7);
+ break;
+ };
+ set_reg(vm, vcpuid, id, va_arg(ap, uint64_t));
+ }
+
+ va_end(ap);
+}
+
+void assert_on_unhandled_exception(struct kvm_vm *vm, uint32_t vcpuid)
+{
+}
diff --git a/tools/testing/selftests/kvm/lib/riscv/ucall.c b/tools/testing/selftests/kvm/lib/riscv/ucall.c
new file mode 100644
index 000000000000..9e42d8248fa6
--- /dev/null
+++ b/tools/testing/selftests/kvm/lib/riscv/ucall.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ucall support. A ucall is a "hypercall to userspace".
+ *
+ * Copyright (C) 2021 Western Digital Corporation or its affiliates.
+ */
+
+#include <linux/kvm.h>
+
+#include "kvm_util.h"
+#include "../kvm_util_internal.h"
+#include "processor.h"
+
+void ucall_init(struct kvm_vm *vm, void *arg)
+{
+}
+
+void ucall_uninit(struct kvm_vm *vm)
+{
+}
+
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5)
+{
+ register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
+ register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
+ register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
+ register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
+ register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
+ register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
+ register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
+ register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
+ struct sbiret ret;
+
+ asm volatile (
+ "ecall"
+ : "+r" (a0), "+r" (a1)
+ : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
+ : "memory");
+ ret.error = a0;
+ ret.value = a1;
+
+ return ret;
+}
+
+void ucall(uint64_t cmd, int nargs, ...)
+{
+ struct ucall uc = {
+ .cmd = cmd,
+ };
+ va_list va;
+ int i;
+
+ nargs = nargs <= UCALL_MAX_ARGS ? nargs : UCALL_MAX_ARGS;
+
+ va_start(va, nargs);
+ for (i = 0; i < nargs; ++i)
+ uc.args[i] = va_arg(va, uint64_t);
+ va_end(va);
+
+ sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT, 0, (vm_vaddr_t)&uc,
+ 0, 0, 0, 0, 0);
+}
+
+uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id, struct ucall *uc)
+{
+ struct kvm_run *run = vcpu_state(vm, vcpu_id);
+ struct ucall ucall = {};
+
+ if (uc)
+ memset(uc, 0, sizeof(*uc));
+
+ if (run->exit_reason == KVM_EXIT_RISCV_SBI &&
+ run->riscv_sbi.extension_id == KVM_RISCV_SELFTESTS_SBI_EXT &&
+ run->riscv_sbi.function_id == 0) {
+ memcpy(&ucall, addr_gva2hva(vm, run->riscv_sbi.args[0]),
+ sizeof(ucall));
+
+ vcpu_run_complete_io(vm, vcpu_id);
+ if (uc)
+ memcpy(uc, &ucall, sizeof(ucall));
+ }
+
+ return ucall.cmd;
+}
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 4/4] KVM: selftests: Add initial support for RISC-V 64-bit
@ 2021-11-29 7:54 ` Anup Patel
0 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-11-29 7:54 UTC (permalink / raw)
To: Paolo Bonzini, Shuah Khan, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
linux-kselftest, Anup Patel
We add initial support for RISC-V 64-bit in KVM selftests using
which we can cross-compile and run arch independent tests such as:
demand_paging_test
dirty_log_test
kvm_create_max_vcpus,
kvm_page_table_test
set_memory_region_test
kvm_binary_stats_test
All VM guest modes defined in kvm_util.h require at least 48-bit
guest virtual address so to use KVM RISC-V selftests hardware
need to support at least Sv48 MMU for guest (i.e. VS-mode).
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
tools/testing/selftests/kvm/Makefile | 12 +
.../testing/selftests/kvm/include/kvm_util.h | 10 +
.../selftests/kvm/include/riscv/processor.h | 135 +++++++
tools/testing/selftests/kvm/lib/guest_modes.c | 10 +
.../selftests/kvm/lib/riscv/processor.c | 362 ++++++++++++++++++
tools/testing/selftests/kvm/lib/riscv/ucall.c | 87 +++++
6 files changed, 616 insertions(+)
create mode 100644 tools/testing/selftests/kvm/include/riscv/processor.h
create mode 100644 tools/testing/selftests/kvm/lib/riscv/processor.c
create mode 100644 tools/testing/selftests/kvm/lib/riscv/ucall.c
diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
index ee6740e9ecdb..2d825d1e7ff2 100644
--- a/tools/testing/selftests/kvm/Makefile
+++ b/tools/testing/selftests/kvm/Makefile
@@ -32,11 +32,16 @@ endif
ifeq ($(ARCH),s390)
UNAME_M := s390x
endif
+# Set UNAME_M riscv compile/install to work
+ifeq ($(ARCH),riscv)
+ UNAME_M := riscv
+endif
LIBKVM = lib/assert.c lib/elf.c lib/io.c lib/kvm_util.c lib/rbtree.c lib/sparsebit.c lib/test_util.c lib/guest_modes.c lib/perf_test_util.c
LIBKVM_x86_64 = lib/x86_64/apic.c lib/x86_64/processor.c lib/x86_64/vmx.c lib/x86_64/svm.c lib/x86_64/ucall.c lib/x86_64/handlers.S
LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S lib/aarch64/spinlock.c lib/aarch64/gic.c lib/aarch64/gic_v3.c lib/aarch64/vgic.c
LIBKVM_s390x = lib/s390x/processor.c lib/s390x/ucall.c lib/s390x/diag318_test_handler.c
+LIBKVM_riscv = lib/riscv/processor.c lib/riscv/ucall.c
TEST_GEN_PROGS_x86_64 = x86_64/cr4_cpuid_sync_test
TEST_GEN_PROGS_x86_64 += x86_64/get_msr_index_features
@@ -117,6 +122,13 @@ TEST_GEN_PROGS_s390x += rseq_test
TEST_GEN_PROGS_s390x += set_memory_region_test
TEST_GEN_PROGS_s390x += kvm_binary_stats_test
+TEST_GEN_PROGS_riscv += demand_paging_test
+TEST_GEN_PROGS_riscv += dirty_log_test
+TEST_GEN_PROGS_riscv += kvm_create_max_vcpus
+TEST_GEN_PROGS_riscv += kvm_page_table_test
+TEST_GEN_PROGS_riscv += set_memory_region_test
+TEST_GEN_PROGS_riscv += kvm_binary_stats_test
+
TEST_GEN_PROGS += $(TEST_GEN_PROGS_$(UNAME_M))
LIBKVM += $(LIBKVM_$(UNAME_M))
diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h
index 6a1a37f30494..c23e5be14862 100644
--- a/tools/testing/selftests/kvm/include/kvm_util.h
+++ b/tools/testing/selftests/kvm/include/kvm_util.h
@@ -69,6 +69,16 @@ enum vm_guest_mode {
#define MIN_PAGE_SHIFT 12U
#define ptes_per_page(page_size) ((page_size) / 16)
+#elif defined(__riscv)
+
+#if __riscv_xlen == 32
+#error "RISC-V 32-bit kvm selftests not supported"
+#endif
+
+#define VM_MODE_DEFAULT VM_MODE_P40V48_4K
+#define MIN_PAGE_SHIFT 12U
+#define ptes_per_page(page_size) ((page_size) / 8)
+
#endif
#define MIN_PAGE_SIZE (1U << MIN_PAGE_SHIFT)
diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
new file mode 100644
index 000000000000..dc284c6bdbc3
--- /dev/null
+++ b/tools/testing/selftests/kvm/include/riscv/processor.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * RISC-V processor specific defines
+ *
+ * Copyright (C) 2021 Western Digital Corporation or its affiliates.
+ */
+#ifndef SELFTEST_KVM_PROCESSOR_H
+#define SELFTEST_KVM_PROCESSOR_H
+
+#include "kvm_util.h"
+#include <linux/stringify.h>
+
+static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx,
+ uint64_t size)
+{
+ return KVM_REG_RISCV | type | idx | size;
+}
+
+#if __riscv_xlen == 64
+#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64
+#else
+#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32
+#endif
+
+#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, \
+ KVM_REG_RISCV_CONFIG_REG(name), \
+ KVM_REG_SIZE_ULONG)
+
+#define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, \
+ KVM_REG_RISCV_CORE_REG(name), \
+ KVM_REG_SIZE_ULONG)
+
+#define RISCV_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \
+ KVM_REG_RISCV_CSR_REG(name), \
+ KVM_REG_SIZE_ULONG)
+
+#define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, \
+ KVM_REG_RISCV_TIMER_REG(name), \
+ KVM_REG_SIZE_U64)
+
+static inline void get_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
+ unsigned long *addr)
+{
+ struct kvm_one_reg reg;
+
+ reg.id = id;
+ reg.addr = (unsigned long)addr;
+ vcpu_get_reg(vm, vcpuid, ®);
+}
+
+static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
+ unsigned long val)
+{
+ struct kvm_one_reg reg;
+
+ reg.id = id;
+ reg.addr = (unsigned long)&val;
+ vcpu_set_reg(vm, vcpuid, ®);
+}
+
+/* L3 index Bit[47:39] */
+#define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL
+#define PGTBL_L3_INDEX_SHIFT 39
+#define PGTBL_L3_BLOCK_SHIFT 39
+#define PGTBL_L3_BLOCK_SIZE 0x0000008000000000ULL
+#define PGTBL_L3_MAP_MASK (~(PGTBL_L3_BLOCK_SIZE - 1))
+/* L2 index Bit[38:30] */
+#define PGTBL_L2_INDEX_MASK 0x0000007FC0000000ULL
+#define PGTBL_L2_INDEX_SHIFT 30
+#define PGTBL_L2_BLOCK_SHIFT 30
+#define PGTBL_L2_BLOCK_SIZE 0x0000000040000000ULL
+#define PGTBL_L2_MAP_MASK (~(PGTBL_L2_BLOCK_SIZE - 1))
+/* L1 index Bit[29:21] */
+#define PGTBL_L1_INDEX_MASK 0x000000003FE00000ULL
+#define PGTBL_L1_INDEX_SHIFT 21
+#define PGTBL_L1_BLOCK_SHIFT 21
+#define PGTBL_L1_BLOCK_SIZE 0x0000000000200000ULL
+#define PGTBL_L1_MAP_MASK (~(PGTBL_L1_BLOCK_SIZE - 1))
+/* L0 index Bit[20:12] */
+#define PGTBL_L0_INDEX_MASK 0x00000000001FF000ULL
+#define PGTBL_L0_INDEX_SHIFT 12
+#define PGTBL_L0_BLOCK_SHIFT 12
+#define PGTBL_L0_BLOCK_SIZE 0x0000000000001000ULL
+#define PGTBL_L0_MAP_MASK (~(PGTBL_L0_BLOCK_SIZE - 1))
+
+#define PGTBL_PTE_ADDR_MASK 0x003FFFFFFFFFFC00ULL
+#define PGTBL_PTE_ADDR_SHIFT 10
+#define PGTBL_PTE_RSW_MASK 0x0000000000000300ULL
+#define PGTBL_PTE_RSW_SHIFT 8
+#define PGTBL_PTE_DIRTY_MASK 0x0000000000000080ULL
+#define PGTBL_PTE_DIRTY_SHIFT 7
+#define PGTBL_PTE_ACCESSED_MASK 0x0000000000000040ULL
+#define PGTBL_PTE_ACCESSED_SHIFT 6
+#define PGTBL_PTE_GLOBAL_MASK 0x0000000000000020ULL
+#define PGTBL_PTE_GLOBAL_SHIFT 5
+#define PGTBL_PTE_USER_MASK 0x0000000000000010ULL
+#define PGTBL_PTE_USER_SHIFT 4
+#define PGTBL_PTE_EXECUTE_MASK 0x0000000000000008ULL
+#define PGTBL_PTE_EXECUTE_SHIFT 3
+#define PGTBL_PTE_WRITE_MASK 0x0000000000000004ULL
+#define PGTBL_PTE_WRITE_SHIFT 2
+#define PGTBL_PTE_READ_MASK 0x0000000000000002ULL
+#define PGTBL_PTE_READ_SHIFT 1
+#define PGTBL_PTE_PERM_MASK (PGTBL_PTE_EXECUTE_MASK | \
+ PGTBL_PTE_WRITE_MASK | \
+ PGTBL_PTE_READ_MASK)
+#define PGTBL_PTE_VALID_MASK 0x0000000000000001ULL
+#define PGTBL_PTE_VALID_SHIFT 0
+
+#define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE
+#define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT
+
+#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
+#define SATP_MODE_39 _AC(0x8000000000000000, UL)
+#define SATP_MODE_48 _AC(0x9000000000000000, UL)
+#define SATP_ASID_BITS 16
+#define SATP_ASID_SHIFT 44
+#define SATP_ASID_MASK _AC(0xFFFF, UL)
+
+#define SBI_EXT_EXPERIMENTAL_START 0x08000000
+#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF
+
+#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END
+
+struct sbiret {
+ long error;
+ long value;
+};
+
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5);
+
+#endif /* SELFTEST_KVM_PROCESSOR_H */
diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/selftests/kvm/lib/guest_modes.c
index c330f414ef96..57839a12e472 100644
--- a/tools/testing/selftests/kvm/lib/guest_modes.c
+++ b/tools/testing/selftests/kvm/lib/guest_modes.c
@@ -38,6 +38,16 @@ void guest_modes_append_default(void)
guest_mode_append(VM_MODE_P47V64_4K, true, true);
}
#endif
+#ifdef __riscv
+ {
+ unsigned int sz = kvm_check_cap(KVM_CAP_VM_GPA_BITS);
+
+ if (sz >= 52)
+ guest_mode_append(VM_MODE_P52V48_4K, true, true);
+ if (sz >= 48)
+ guest_mode_append(VM_MODE_P48V48_4K, true, true);
+ }
+#endif
}
void for_each_guest_mode(void (*func)(enum vm_guest_mode, void *), void *arg)
diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
new file mode 100644
index 000000000000..d377f2603d98
--- /dev/null
+++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RISC-V code
+ *
+ * Copyright (C) 2021 Western Digital Corporation or its affiliates.
+ */
+
+#include <linux/compiler.h>
+#include <assert.h>
+
+#include "kvm_util.h"
+#include "../kvm_util_internal.h"
+#include "processor.h"
+
+#define DEFAULT_RISCV_GUEST_STACK_VADDR_MIN 0xac0000
+
+static uint64_t page_align(struct kvm_vm *vm, uint64_t v)
+{
+ return (v + vm->page_size) & ~(vm->page_size - 1);
+}
+
+static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry)
+{
+ return ((entry & PGTBL_PTE_ADDR_MASK) >> PGTBL_PTE_ADDR_SHIFT) <<
+ PGTBL_PAGE_SIZE_SHIFT;
+}
+
+static uint64_t ptrs_per_pte(struct kvm_vm *vm)
+{
+ return PGTBL_PAGE_SIZE / sizeof(uint64_t);
+}
+
+static uint64_t pte_index_mask[] = {
+ PGTBL_L0_INDEX_MASK,
+ PGTBL_L1_INDEX_MASK,
+ PGTBL_L2_INDEX_MASK,
+ PGTBL_L3_INDEX_MASK,
+};
+
+static uint32_t pte_index_shift[] = {
+ PGTBL_L0_INDEX_SHIFT,
+ PGTBL_L1_INDEX_SHIFT,
+ PGTBL_L2_INDEX_SHIFT,
+ PGTBL_L3_INDEX_SHIFT,
+};
+
+static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level)
+{
+ TEST_ASSERT(level > -1,
+ "Negative page table level (%d) not possible", level);
+ TEST_ASSERT(level < vm->pgtable_levels,
+ "Invalid page table level (%d)", level);
+
+ return (gva & pte_index_mask[level]) >> pte_index_shift[level];
+}
+
+void virt_pgd_alloc(struct kvm_vm *vm)
+{
+ if (!vm->pgd_created) {
+ vm_paddr_t paddr = vm_phy_pages_alloc(vm,
+ page_align(vm, ptrs_per_pte(vm) * 8) / vm->page_size,
+ KVM_GUEST_PAGE_TABLE_MIN_PADDR, 0);
+ vm->pgd = paddr;
+ vm->pgd_created = true;
+ }
+}
+
+void virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
+{
+ uint64_t *ptep, next_ppn;
+ int level = vm->pgtable_levels - 1;
+
+ TEST_ASSERT((vaddr % vm->page_size) == 0,
+ "Virtual address not on page boundary,\n"
+ " vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size);
+ TEST_ASSERT(sparsebit_is_set(vm->vpages_valid,
+ (vaddr >> vm->page_shift)),
+ "Invalid virtual address, vaddr: 0x%lx", vaddr);
+ TEST_ASSERT((paddr % vm->page_size) == 0,
+ "Physical address not on page boundary,\n"
+ " paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size);
+ TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
+ "Physical address beyond maximum supported,\n"
+ " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
+ paddr, vm->max_gfn, vm->page_size);
+
+ ptep = addr_gpa2hva(vm, vm->pgd) + pte_index(vm, vaddr, level) * 8;
+ if (!*ptep) {
+ next_ppn = vm_alloc_page_table(vm) >> PGTBL_PAGE_SIZE_SHIFT;
+ *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) |
+ PGTBL_PTE_VALID_MASK;
+ }
+ level--;
+
+ while (level > -1) {
+ ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) +
+ pte_index(vm, vaddr, level) * 8;
+ if (!*ptep && level > 0) {
+ next_ppn = vm_alloc_page_table(vm) >>
+ PGTBL_PAGE_SIZE_SHIFT;
+ *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) |
+ PGTBL_PTE_VALID_MASK;
+ }
+ level--;
+ }
+
+ paddr = paddr >> PGTBL_PAGE_SIZE_SHIFT;
+ *ptep = (paddr << PGTBL_PTE_ADDR_SHIFT) |
+ PGTBL_PTE_PERM_MASK | PGTBL_PTE_VALID_MASK;
+}
+
+vm_paddr_t addr_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
+{
+ uint64_t *ptep;
+ int level = vm->pgtable_levels - 1;
+
+ if (!vm->pgd_created)
+ goto unmapped_gva;
+
+ ptep = addr_gpa2hva(vm, vm->pgd) + pte_index(vm, gva, level) * 8;
+ if (!ptep)
+ goto unmapped_gva;
+ level--;
+
+ while (level > -1) {
+ ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) +
+ pte_index(vm, gva, level) * 8;
+ if (!ptep)
+ goto unmapped_gva;
+ level--;
+ }
+
+ return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1));
+
+unmapped_gva:
+ TEST_FAIL("No mapping for vm virtual address gva: 0x%lx level: %d",
+ gva, level);
+ exit(1);
+}
+
+static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent,
+ uint64_t page, int level)
+{
+#ifdef DEBUG
+ static const char *const type[] = { "pte", "pmd", "pud", "p4d"};
+ uint64_t pte, *ptep;
+
+ if (level < 0)
+ return;
+
+ for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) {
+ ptep = addr_gpa2hva(vm, pte);
+ if (!*ptep)
+ continue;
+ fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "",
+ type[level], pte, *ptep, ptep);
+ pte_dump(stream, vm, indent + 1,
+ pte_addr(vm, *ptep), level - 1);
+ }
+#endif
+}
+
+void virt_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
+{
+ int level = vm->pgtable_levels - 1;
+ uint64_t pgd, *ptep;
+
+ if (!vm->pgd_created)
+ return;
+
+ for (pgd = vm->pgd; pgd < vm->pgd + ptrs_per_pte(vm) * 8; pgd += 8) {
+ ptep = addr_gpa2hva(vm, pgd);
+ if (!*ptep)
+ continue;
+ fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "",
+ pgd, *ptep, ptep);
+ pte_dump(stream, vm, indent + 1,
+ pte_addr(vm, *ptep), level - 1);
+ }
+}
+
+void riscv_vcpu_mmu_setup(struct kvm_vm *vm, int vcpuid)
+{
+ unsigned long satp;
+
+ /*
+ * The RISC-V Sv48 MMU mode supports 56-bit physical address
+ * for 48-bit virtual address with 4KB last level page size.
+ */
+ switch (vm->mode) {
+ case VM_MODE_P52V48_4K:
+ case VM_MODE_P48V48_4K:
+ case VM_MODE_P40V48_4K:
+ break;
+ default:
+ TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode);
+ }
+
+ satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN;
+ satp |= SATP_MODE_48;
+
+ set_reg(vm, vcpuid, RISCV_CSR_REG(satp), satp);
+}
+
+void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint8_t indent)
+{
+ struct kvm_riscv_core core;
+
+ get_reg(vm, vcpuid, RISCV_CORE_REG(mode), &core.mode);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.pc), &core.regs.pc);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.ra), &core.regs.ra);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.sp), &core.regs.sp);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.gp), &core.regs.gp);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.tp), &core.regs.tp);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t0), &core.regs.t0);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t1), &core.regs.t1);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t2), &core.regs.t2);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s0), &core.regs.s0);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s1), &core.regs.s1);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a0), &core.regs.a0);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a1), &core.regs.a1);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a2), &core.regs.a2);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a3), &core.regs.a3);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a4), &core.regs.a4);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a5), &core.regs.a5);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a6), &core.regs.a6);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a7), &core.regs.a7);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s2), &core.regs.s2);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s3), &core.regs.s3);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s4), &core.regs.s4);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s5), &core.regs.s5);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s6), &core.regs.s6);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s7), &core.regs.s7);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s8), &core.regs.s8);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s9), &core.regs.s9);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s10), &core.regs.s10);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s11), &core.regs.s11);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t3), &core.regs.t3);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t4), &core.regs.t4);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t5), &core.regs.t5);
+ get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t6), &core.regs.t6);
+
+ fprintf(stream,
+ " MODE: 0x%lx\n", core.mode);
+ fprintf(stream,
+ " PC: 0x%016lx RA: 0x%016lx SP: 0x%016lx GP: 0x%016lx\n",
+ core.regs.pc, core.regs.ra, core.regs.sp, core.regs.gp);
+ fprintf(stream,
+ " TP: 0x%016lx T0: 0x%016lx T1: 0x%016lx T2: 0x%016lx\n",
+ core.regs.tp, core.regs.t0, core.regs.t1, core.regs.t2);
+ fprintf(stream,
+ " S0: 0x%016lx S1: 0x%016lx A0: 0x%016lx A1: 0x%016lx\n",
+ core.regs.s0, core.regs.s1, core.regs.a0, core.regs.a1);
+ fprintf(stream,
+ " A2: 0x%016lx A3: 0x%016lx A4: 0x%016lx A5: 0x%016lx\n",
+ core.regs.a2, core.regs.a3, core.regs.a4, core.regs.a5);
+ fprintf(stream,
+ " A6: 0x%016lx A7: 0x%016lx S2: 0x%016lx S3: 0x%016lx\n",
+ core.regs.a6, core.regs.a7, core.regs.s2, core.regs.s3);
+ fprintf(stream,
+ " S4: 0x%016lx S5: 0x%016lx S6: 0x%016lx S7: 0x%016lx\n",
+ core.regs.s4, core.regs.s5, core.regs.s6, core.regs.s7);
+ fprintf(stream,
+ " S8: 0x%016lx S9: 0x%016lx S10: 0x%016lx S11: 0x%016lx\n",
+ core.regs.s8, core.regs.s9, core.regs.s10, core.regs.s11);
+ fprintf(stream,
+ " T3: 0x%016lx T4: 0x%016lx T5: 0x%016lx T6: 0x%016lx\n",
+ core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6);
+}
+
+static void guest_hang(void)
+{
+ while (1)
+ ;
+}
+
+void vm_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, void *guest_code)
+{
+ int r;
+ size_t stack_size = vm->page_size == 4096 ?
+ DEFAULT_STACK_PGS * vm->page_size :
+ vm->page_size;
+ unsigned long stack_vaddr = vm_vaddr_alloc(vm, stack_size,
+ DEFAULT_RISCV_GUEST_STACK_VADDR_MIN);
+ unsigned long current_gp = 0;
+ struct kvm_mp_state mps;
+
+ vm_vcpu_add(vm, vcpuid);
+ riscv_vcpu_mmu_setup(vm, vcpuid);
+
+ /*
+ * With SBI HSM support in KVM RISC-V, all secondary VCPUs are
+ * powered-off by default so we ensure that all secondary VCPUs
+ * are powered-on using KVM_SET_MP_STATE ioctl().
+ */
+ mps.mp_state = KVM_MP_STATE_RUNNABLE;
+ r = _vcpu_ioctl(vm, vcpuid, KVM_SET_MP_STATE, &mps);
+ TEST_ASSERT(!r, "IOCTL KVM_SET_MP_STATE failed (error %d)", r);
+
+ /* Setup global pointer of guest to be same as the host */
+ asm volatile (
+ "add %0, gp, zero" : "=r" (current_gp) : : "memory");
+ set_reg(vm, vcpuid, RISCV_CORE_REG(regs.gp), current_gp);
+
+ /* Setup stack pointer and program counter of guest */
+ set_reg(vm, vcpuid, RISCV_CORE_REG(regs.sp),
+ stack_vaddr + stack_size);
+ set_reg(vm, vcpuid, RISCV_CORE_REG(regs.pc),
+ (unsigned long)guest_code);
+
+ /* Setup default exception vector of guest */
+ set_reg(vm, vcpuid, RISCV_CSR_REG(stvec),
+ (unsigned long)guest_hang);
+}
+
+void vcpu_args_set(struct kvm_vm *vm, uint32_t vcpuid, unsigned int num, ...)
+{
+ va_list ap;
+ uint64_t id = RISCV_CORE_REG(regs.a0);
+ int i;
+
+ TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n"
+ " num: %u\n", num);
+
+ va_start(ap, num);
+
+ for (i = 0; i < num; i++) {
+ switch (i) {
+ case 0:
+ id = RISCV_CORE_REG(regs.a0);
+ break;
+ case 1:
+ id = RISCV_CORE_REG(regs.a1);
+ break;
+ case 2:
+ id = RISCV_CORE_REG(regs.a2);
+ break;
+ case 3:
+ id = RISCV_CORE_REG(regs.a3);
+ break;
+ case 4:
+ id = RISCV_CORE_REG(regs.a4);
+ break;
+ case 5:
+ id = RISCV_CORE_REG(regs.a5);
+ break;
+ case 6:
+ id = RISCV_CORE_REG(regs.a6);
+ break;
+ case 7:
+ id = RISCV_CORE_REG(regs.a7);
+ break;
+ };
+ set_reg(vm, vcpuid, id, va_arg(ap, uint64_t));
+ }
+
+ va_end(ap);
+}
+
+void assert_on_unhandled_exception(struct kvm_vm *vm, uint32_t vcpuid)
+{
+}
diff --git a/tools/testing/selftests/kvm/lib/riscv/ucall.c b/tools/testing/selftests/kvm/lib/riscv/ucall.c
new file mode 100644
index 000000000000..9e42d8248fa6
--- /dev/null
+++ b/tools/testing/selftests/kvm/lib/riscv/ucall.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ucall support. A ucall is a "hypercall to userspace".
+ *
+ * Copyright (C) 2021 Western Digital Corporation or its affiliates.
+ */
+
+#include <linux/kvm.h>
+
+#include "kvm_util.h"
+#include "../kvm_util_internal.h"
+#include "processor.h"
+
+void ucall_init(struct kvm_vm *vm, void *arg)
+{
+}
+
+void ucall_uninit(struct kvm_vm *vm)
+{
+}
+
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+ unsigned long arg1, unsigned long arg2,
+ unsigned long arg3, unsigned long arg4,
+ unsigned long arg5)
+{
+ register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
+ register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
+ register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
+ register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
+ register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
+ register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
+ register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
+ register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
+ struct sbiret ret;
+
+ asm volatile (
+ "ecall"
+ : "+r" (a0), "+r" (a1)
+ : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
+ : "memory");
+ ret.error = a0;
+ ret.value = a1;
+
+ return ret;
+}
+
+void ucall(uint64_t cmd, int nargs, ...)
+{
+ struct ucall uc = {
+ .cmd = cmd,
+ };
+ va_list va;
+ int i;
+
+ nargs = nargs <= UCALL_MAX_ARGS ? nargs : UCALL_MAX_ARGS;
+
+ va_start(va, nargs);
+ for (i = 0; i < nargs; ++i)
+ uc.args[i] = va_arg(va, uint64_t);
+ va_end(va);
+
+ sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT, 0, (vm_vaddr_t)&uc,
+ 0, 0, 0, 0, 0);
+}
+
+uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id, struct ucall *uc)
+{
+ struct kvm_run *run = vcpu_state(vm, vcpu_id);
+ struct ucall ucall = {};
+
+ if (uc)
+ memset(uc, 0, sizeof(*uc));
+
+ if (run->exit_reason == KVM_EXIT_RISCV_SBI &&
+ run->riscv_sbi.extension_id == KVM_RISCV_SELFTESTS_SBI_EXT &&
+ run->riscv_sbi.function_id == 0) {
+ memcpy(&ucall, addr_gva2hva(vm, run->riscv_sbi.args[0]),
+ sizeof(ucall));
+
+ vcpu_run_complete_io(vm, vcpu_id);
+ if (uc)
+ memcpy(uc, &ucall, sizeof(ucall));
+ }
+
+ return ucall.cmd;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v2 0/4] KVM RISC-V 64-bit selftests support
2021-11-29 7:54 ` Anup Patel
@ 2021-12-11 3:41 ` Anup Patel
-1 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-12-11 3:41 UTC (permalink / raw)
To: Paolo Bonzini
Cc: Shuah Khan, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Alistair Francis, KVM General, kvm-riscv, linux-riscv,
linux-kernel@vger.kernel.org List, linux-kselftest, Anup Patel
Hi Paolo,
On Mon, Nov 29, 2021 at 1:40 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> This series adds initial support for testing KVM RISC-V 64-bit using
> kernel selftests framework. The PATCH1 & PATCH2 of this series does
> some ground work in KVM RISC-V to implement RISC-V support in the KVM
> selftests whereas remaining patches does required changes in the KVM
> selftests.
>
> These patches can be found in riscv_kvm_selftests_v2 branch at:
> https://github.com/avpatel/linux.git
>
> Changes since v1:
> - Renamed kvm_sbi_ext_expevend_handler() to kvm_sbi_ext_forward_handler()
> in PATCH1
> - Renamed KVM_CAP_RISCV_VM_GPA_SIZE to KVM_CAP_VM_GPA_BITS in PATCH2
> and PATCH4
>
> Anup Patel (4):
> RISC-V: KVM: Forward SBI experimental and vendor extensions
> RISC-V: KVM: Add VM capability to allow userspace get GPA bits
> KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
> KVM: selftests: Add initial support for RISC-V 64-bit
Any further comments on this series ?
Regards,
Anup
>
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/kvm/mmu.c | 5 +
> arch/riscv/kvm/vcpu_sbi.c | 4 +
> arch/riscv/kvm/vcpu_sbi_base.c | 27 ++
> arch/riscv/kvm/vm.c | 3 +
> include/uapi/linux/kvm.h | 1 +
> tools/testing/selftests/kvm/Makefile | 14 +-
> .../testing/selftests/kvm/include/kvm_util.h | 10 +
> .../selftests/kvm/include/riscv/processor.h | 135 +++++++
> tools/testing/selftests/kvm/lib/guest_modes.c | 10 +
> .../selftests/kvm/lib/riscv/processor.c | 362 ++++++++++++++++++
> tools/testing/selftests/kvm/lib/riscv/ucall.c | 87 +++++
> 12 files changed, 658 insertions(+), 1 deletion(-)
> create mode 100644 tools/testing/selftests/kvm/include/riscv/processor.h
> create mode 100644 tools/testing/selftests/kvm/lib/riscv/processor.c
> create mode 100644 tools/testing/selftests/kvm/lib/riscv/ucall.c
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 0/4] KVM RISC-V 64-bit selftests support
@ 2021-12-11 3:41 ` Anup Patel
0 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-12-11 3:41 UTC (permalink / raw)
To: Paolo Bonzini
Cc: Shuah Khan, Atish Patra, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Alistair Francis, KVM General, kvm-riscv, linux-riscv,
linux-kernel@vger.kernel.org List, linux-kselftest, Anup Patel
Hi Paolo,
On Mon, Nov 29, 2021 at 1:40 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> This series adds initial support for testing KVM RISC-V 64-bit using
> kernel selftests framework. The PATCH1 & PATCH2 of this series does
> some ground work in KVM RISC-V to implement RISC-V support in the KVM
> selftests whereas remaining patches does required changes in the KVM
> selftests.
>
> These patches can be found in riscv_kvm_selftests_v2 branch at:
> https://github.com/avpatel/linux.git
>
> Changes since v1:
> - Renamed kvm_sbi_ext_expevend_handler() to kvm_sbi_ext_forward_handler()
> in PATCH1
> - Renamed KVM_CAP_RISCV_VM_GPA_SIZE to KVM_CAP_VM_GPA_BITS in PATCH2
> and PATCH4
>
> Anup Patel (4):
> RISC-V: KVM: Forward SBI experimental and vendor extensions
> RISC-V: KVM: Add VM capability to allow userspace get GPA bits
> KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
> KVM: selftests: Add initial support for RISC-V 64-bit
Any further comments on this series ?
Regards,
Anup
>
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/kvm/mmu.c | 5 +
> arch/riscv/kvm/vcpu_sbi.c | 4 +
> arch/riscv/kvm/vcpu_sbi_base.c | 27 ++
> arch/riscv/kvm/vm.c | 3 +
> include/uapi/linux/kvm.h | 1 +
> tools/testing/selftests/kvm/Makefile | 14 +-
> .../testing/selftests/kvm/include/kvm_util.h | 10 +
> .../selftests/kvm/include/riscv/processor.h | 135 +++++++
> tools/testing/selftests/kvm/lib/guest_modes.c | 10 +
> .../selftests/kvm/lib/riscv/processor.c | 362 ++++++++++++++++++
> tools/testing/selftests/kvm/lib/riscv/ucall.c | 87 +++++
> 12 files changed, 658 insertions(+), 1 deletion(-)
> create mode 100644 tools/testing/selftests/kvm/include/riscv/processor.h
> create mode 100644 tools/testing/selftests/kvm/lib/riscv/processor.c
> create mode 100644 tools/testing/selftests/kvm/lib/riscv/ucall.c
>
> --
> 2.25.1
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 1/4] RISC-V: KVM: Forward SBI experimental and vendor extensions
2021-11-29 7:54 ` Anup Patel
@ 2021-12-17 5:42 ` Atish Patra
-1 siblings, 0 replies; 30+ messages in thread
From: Atish Patra @ 2021-12-17 5:42 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Shuah Khan, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Alistair Francis, Anup Patel, KVM General, kvm-riscv,
linux-riscv, linux-kernel@vger.kernel.org List, linux-kselftest
On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The SBI experimental extension space is for temporary (or experimental)
> stuff whereas SBI vendor extension space is for hardware vendor specific
> stuff. Both these SBI extension spaces won't be standardized by the SBI
> specification so let's blindly forward such SBI calls to the userspace.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> arch/riscv/kvm/vcpu_sbi.c | 4 ++++
> arch/riscv/kvm/vcpu_sbi_base.c | 27 +++++++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
> index f62d25bc9733..78aa3db76225 100644
> --- a/arch/riscv/kvm/vcpu_sbi.c
> +++ b/arch/riscv/kvm/vcpu_sbi.c
> @@ -46,6 +46,8 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time;
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi;
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence;
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm;
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental;
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor;
>
> static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> &vcpu_sbi_ext_v01,
> @@ -54,6 +56,8 @@ static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> &vcpu_sbi_ext_ipi,
> &vcpu_sbi_ext_rfence,
> &vcpu_sbi_ext_hsm,
> + &vcpu_sbi_ext_experimental,
> + &vcpu_sbi_ext_vendor,
> };
>
> void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run)
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 641015549d12..ac0537d479d8 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -68,3 +68,30 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_base = {
> .extid_end = SBI_EXT_BASE,
> .handler = kvm_sbi_ext_base_handler,
> };
> +
> +static int kvm_sbi_ext_forward_handler(struct kvm_vcpu *vcpu,
> + struct kvm_run *run,
> + unsigned long *out_val,
> + struct kvm_cpu_trap *utrap,
> + bool *exit)
> +{
> + /*
> + * Both SBI experimental and vendor extensions are
> + * unconditionally forwarded to userspace.
> + */
> + kvm_riscv_vcpu_sbi_forward(vcpu, run);
> + *exit = true;
> + return 0;
> +}
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental = {
> + .extid_start = SBI_EXT_EXPERIMENTAL_START,
> + .extid_end = SBI_EXT_EXPERIMENTAL_END,
> + .handler = kvm_sbi_ext_forward_handler,
> +};
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor = {
> + .extid_start = SBI_EXT_VENDOR_START,
> + .extid_end = SBI_EXT_VENDOR_END,
> + .handler = kvm_sbi_ext_forward_handler,
> +};
> --
> 2.25.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
--
Regards,
Atish
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 1/4] RISC-V: KVM: Forward SBI experimental and vendor extensions
@ 2021-12-17 5:42 ` Atish Patra
0 siblings, 0 replies; 30+ messages in thread
From: Atish Patra @ 2021-12-17 5:42 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Shuah Khan, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Alistair Francis, Anup Patel, KVM General, kvm-riscv,
linux-riscv, linux-kernel@vger.kernel.org List, linux-kselftest
On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The SBI experimental extension space is for temporary (or experimental)
> stuff whereas SBI vendor extension space is for hardware vendor specific
> stuff. Both these SBI extension spaces won't be standardized by the SBI
> specification so let's blindly forward such SBI calls to the userspace.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> arch/riscv/kvm/vcpu_sbi.c | 4 ++++
> arch/riscv/kvm/vcpu_sbi_base.c | 27 +++++++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
> index f62d25bc9733..78aa3db76225 100644
> --- a/arch/riscv/kvm/vcpu_sbi.c
> +++ b/arch/riscv/kvm/vcpu_sbi.c
> @@ -46,6 +46,8 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_time;
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi;
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence;
> extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm;
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental;
> +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor;
>
> static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> &vcpu_sbi_ext_v01,
> @@ -54,6 +56,8 @@ static const struct kvm_vcpu_sbi_extension *sbi_ext[] = {
> &vcpu_sbi_ext_ipi,
> &vcpu_sbi_ext_rfence,
> &vcpu_sbi_ext_hsm,
> + &vcpu_sbi_ext_experimental,
> + &vcpu_sbi_ext_vendor,
> };
>
> void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run)
> diff --git a/arch/riscv/kvm/vcpu_sbi_base.c b/arch/riscv/kvm/vcpu_sbi_base.c
> index 641015549d12..ac0537d479d8 100644
> --- a/arch/riscv/kvm/vcpu_sbi_base.c
> +++ b/arch/riscv/kvm/vcpu_sbi_base.c
> @@ -68,3 +68,30 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_base = {
> .extid_end = SBI_EXT_BASE,
> .handler = kvm_sbi_ext_base_handler,
> };
> +
> +static int kvm_sbi_ext_forward_handler(struct kvm_vcpu *vcpu,
> + struct kvm_run *run,
> + unsigned long *out_val,
> + struct kvm_cpu_trap *utrap,
> + bool *exit)
> +{
> + /*
> + * Both SBI experimental and vendor extensions are
> + * unconditionally forwarded to userspace.
> + */
> + kvm_riscv_vcpu_sbi_forward(vcpu, run);
> + *exit = true;
> + return 0;
> +}
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental = {
> + .extid_start = SBI_EXT_EXPERIMENTAL_START,
> + .extid_end = SBI_EXT_EXPERIMENTAL_END,
> + .handler = kvm_sbi_ext_forward_handler,
> +};
> +
> +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor = {
> + .extid_start = SBI_EXT_VENDOR_START,
> + .extid_end = SBI_EXT_VENDOR_END,
> + .handler = kvm_sbi_ext_forward_handler,
> +};
> --
> 2.25.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA bits
2021-11-29 7:54 ` Anup Patel
@ 2021-12-17 5:47 ` Atish Patra
-1 siblings, 0 replies; 30+ messages in thread
From: Atish Patra @ 2021-12-17 5:47 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Shuah Khan, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Alistair Francis, Anup Patel, KVM General, kvm-riscv,
linux-riscv, linux-kernel@vger.kernel.org List, linux-kselftest
On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The number of GPA bits supported for a RISC-V Guest/VM is based on the
> MMU mode used by the G-stage translation. The KVM RISC-V will detect and
> use the best possible MMU mode for the G-stage in kvm_arch_init().
>
> We add a generic VM capability KVM_CAP_VM_GPA_BITS which can be used by
> the KVM userspace to get the number of GPA (guest physical address) bits
> supported for a Guest/VM.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/kvm/mmu.c | 5 +++++
> arch/riscv/kvm/vm.c | 3 +++
> include/uapi/linux/kvm.h | 1 +
> 4 files changed, 10 insertions(+)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index 37589b953bcb..ae5d238607fe 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -221,6 +221,7 @@ void kvm_riscv_stage2_free_pgd(struct kvm *kvm);
> void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu);
> void kvm_riscv_stage2_mode_detect(void);
> unsigned long kvm_riscv_stage2_mode(void);
> +int kvm_riscv_stage2_gpa_size(void);
>
> void kvm_riscv_stage2_vmid_detect(void);
> unsigned long kvm_riscv_stage2_vmid_bits(void);
> diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
> index 9ffd0255af43..9b6d6465094f 100644
> --- a/arch/riscv/kvm/mmu.c
> +++ b/arch/riscv/kvm/mmu.c
> @@ -760,3 +760,8 @@ unsigned long kvm_riscv_stage2_mode(void)
> {
> return stage2_mode >> HGATP_MODE_SHIFT;
> }
> +
> +int kvm_riscv_stage2_gpa_size(void)
> +{
> + return stage2_gpa_bits;
> +}
The ioctl & the underlying stage2_gpa_bits has bits.
Maybe rename the function to kvm_riscv_stage2_gpa_bits as well ?
> diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c
> index fb18af34a4b5..6f959639ec45 100644
> --- a/arch/riscv/kvm/vm.c
> +++ b/arch/riscv/kvm/vm.c
> @@ -82,6 +82,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
> case KVM_CAP_NR_MEMSLOTS:
> r = KVM_USER_MEM_SLOTS;
> break;
> + case KVM_CAP_VM_GPA_BITS:
> + r = kvm_riscv_stage2_gpa_size();
> + break;
> default:
> r = 0;
> break;
> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
> index 1daa45268de2..469f05d69c8d 100644
> --- a/include/uapi/linux/kvm.h
> +++ b/include/uapi/linux/kvm.h
> @@ -1131,6 +1131,7 @@ struct kvm_ppc_resize_hpt {
> #define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204
> #define KVM_CAP_ARM_MTE 205
> #define KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM 206
> +#define KVM_CAP_VM_GPA_BITS 207
>
> #ifdef KVM_CAP_IRQ_ROUTING
>
> --
> 2.25.1
>
Other than that, it looks good to me.
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA bits
@ 2021-12-17 5:47 ` Atish Patra
0 siblings, 0 replies; 30+ messages in thread
From: Atish Patra @ 2021-12-17 5:47 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Shuah Khan, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Alistair Francis, Anup Patel, KVM General, kvm-riscv,
linux-riscv, linux-kernel@vger.kernel.org List, linux-kselftest
On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The number of GPA bits supported for a RISC-V Guest/VM is based on the
> MMU mode used by the G-stage translation. The KVM RISC-V will detect and
> use the best possible MMU mode for the G-stage in kvm_arch_init().
>
> We add a generic VM capability KVM_CAP_VM_GPA_BITS which can be used by
> the KVM userspace to get the number of GPA (guest physical address) bits
> supported for a Guest/VM.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/kvm/mmu.c | 5 +++++
> arch/riscv/kvm/vm.c | 3 +++
> include/uapi/linux/kvm.h | 1 +
> 4 files changed, 10 insertions(+)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index 37589b953bcb..ae5d238607fe 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -221,6 +221,7 @@ void kvm_riscv_stage2_free_pgd(struct kvm *kvm);
> void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu);
> void kvm_riscv_stage2_mode_detect(void);
> unsigned long kvm_riscv_stage2_mode(void);
> +int kvm_riscv_stage2_gpa_size(void);
>
> void kvm_riscv_stage2_vmid_detect(void);
> unsigned long kvm_riscv_stage2_vmid_bits(void);
> diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
> index 9ffd0255af43..9b6d6465094f 100644
> --- a/arch/riscv/kvm/mmu.c
> +++ b/arch/riscv/kvm/mmu.c
> @@ -760,3 +760,8 @@ unsigned long kvm_riscv_stage2_mode(void)
> {
> return stage2_mode >> HGATP_MODE_SHIFT;
> }
> +
> +int kvm_riscv_stage2_gpa_size(void)
> +{
> + return stage2_gpa_bits;
> +}
The ioctl & the underlying stage2_gpa_bits has bits.
Maybe rename the function to kvm_riscv_stage2_gpa_bits as well ?
> diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c
> index fb18af34a4b5..6f959639ec45 100644
> --- a/arch/riscv/kvm/vm.c
> +++ b/arch/riscv/kvm/vm.c
> @@ -82,6 +82,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
> case KVM_CAP_NR_MEMSLOTS:
> r = KVM_USER_MEM_SLOTS;
> break;
> + case KVM_CAP_VM_GPA_BITS:
> + r = kvm_riscv_stage2_gpa_size();
> + break;
> default:
> r = 0;
> break;
> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
> index 1daa45268de2..469f05d69c8d 100644
> --- a/include/uapi/linux/kvm.h
> +++ b/include/uapi/linux/kvm.h
> @@ -1131,6 +1131,7 @@ struct kvm_ppc_resize_hpt {
> #define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204
> #define KVM_CAP_ARM_MTE 205
> #define KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM 206
> +#define KVM_CAP_VM_GPA_BITS 207
>
> #ifdef KVM_CAP_IRQ_ROUTING
>
> --
> 2.25.1
>
Other than that, it looks good to me.
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 3/4] KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
2021-11-29 7:54 ` Anup Patel
@ 2021-12-17 5:50 ` Atish Patra
-1 siblings, 0 replies; 30+ messages in thread
From: Atish Patra @ 2021-12-17 5:50 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Shuah Khan, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Alistair Francis, Anup Patel, KVM General, kvm-riscv,
linux-riscv, linux-kernel@vger.kernel.org List, linux-kselftest
On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> We add EXTRA_CFLAGS to the common CFLAGS of top-level Makefile
> which will allow users to pass additional compile-time flags such
> as "-static".
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> tools/testing/selftests/kvm/Makefile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
> index c4e34717826a..ee6740e9ecdb 100644
> --- a/tools/testing/selftests/kvm/Makefile
> +++ b/tools/testing/selftests/kvm/Makefile
> @@ -131,7 +131,7 @@ endif
> CFLAGS += -Wall -Wstrict-prototypes -Wuninitialized -O2 -g -std=gnu99 \
> -fno-stack-protector -fno-PIE -I$(LINUX_TOOL_INCLUDE) \
> -I$(LINUX_TOOL_ARCH_INCLUDE) -I$(LINUX_HDR_PATH) -Iinclude \
> - -I$(<D) -Iinclude/$(UNAME_M) -I..
> + -I$(<D) -Iinclude/$(UNAME_M) -I.. $(EXTRA_CFLAGS)
>
> no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
> $(CC) -Werror -no-pie -x c - -o "$$TMP", -no-pie)
> --
> 2.25.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
--
Regards,
Atish
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 3/4] KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
@ 2021-12-17 5:50 ` Atish Patra
0 siblings, 0 replies; 30+ messages in thread
From: Atish Patra @ 2021-12-17 5:50 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Shuah Khan, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Alistair Francis, Anup Patel, KVM General, kvm-riscv,
linux-riscv, linux-kernel@vger.kernel.org List, linux-kselftest
On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> We add EXTRA_CFLAGS to the common CFLAGS of top-level Makefile
> which will allow users to pass additional compile-time flags such
> as "-static".
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> tools/testing/selftests/kvm/Makefile | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
> index c4e34717826a..ee6740e9ecdb 100644
> --- a/tools/testing/selftests/kvm/Makefile
> +++ b/tools/testing/selftests/kvm/Makefile
> @@ -131,7 +131,7 @@ endif
> CFLAGS += -Wall -Wstrict-prototypes -Wuninitialized -O2 -g -std=gnu99 \
> -fno-stack-protector -fno-PIE -I$(LINUX_TOOL_INCLUDE) \
> -I$(LINUX_TOOL_ARCH_INCLUDE) -I$(LINUX_HDR_PATH) -Iinclude \
> - -I$(<D) -Iinclude/$(UNAME_M) -I..
> + -I$(<D) -Iinclude/$(UNAME_M) -I.. $(EXTRA_CFLAGS)
>
> no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
> $(CC) -Werror -no-pie -x c - -o "$$TMP", -no-pie)
> --
> 2.25.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA bits
2021-12-17 5:47 ` Atish Patra
@ 2021-12-17 6:08 ` Anup Patel
-1 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-12-17 6:08 UTC (permalink / raw)
To: Atish Patra
Cc: Anup Patel, Paolo Bonzini, Shuah Khan, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Alistair Francis, KVM General,
kvm-riscv, linux-riscv, linux-kernel@vger.kernel.org List,
linux-kselftest
On Fri, Dec 17, 2021 at 11:17 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > The number of GPA bits supported for a RISC-V Guest/VM is based on the
> > MMU mode used by the G-stage translation. The KVM RISC-V will detect and
> > use the best possible MMU mode for the G-stage in kvm_arch_init().
> >
> > We add a generic VM capability KVM_CAP_VM_GPA_BITS which can be used by
> > the KVM userspace to get the number of GPA (guest physical address) bits
> > supported for a Guest/VM.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > arch/riscv/include/asm/kvm_host.h | 1 +
> > arch/riscv/kvm/mmu.c | 5 +++++
> > arch/riscv/kvm/vm.c | 3 +++
> > include/uapi/linux/kvm.h | 1 +
> > 4 files changed, 10 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> > index 37589b953bcb..ae5d238607fe 100644
> > --- a/arch/riscv/include/asm/kvm_host.h
> > +++ b/arch/riscv/include/asm/kvm_host.h
> > @@ -221,6 +221,7 @@ void kvm_riscv_stage2_free_pgd(struct kvm *kvm);
> > void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu);
> > void kvm_riscv_stage2_mode_detect(void);
> > unsigned long kvm_riscv_stage2_mode(void);
> > +int kvm_riscv_stage2_gpa_size(void);
> >
> > void kvm_riscv_stage2_vmid_detect(void);
> > unsigned long kvm_riscv_stage2_vmid_bits(void);
> > diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
> > index 9ffd0255af43..9b6d6465094f 100644
> > --- a/arch/riscv/kvm/mmu.c
> > +++ b/arch/riscv/kvm/mmu.c
> > @@ -760,3 +760,8 @@ unsigned long kvm_riscv_stage2_mode(void)
> > {
> > return stage2_mode >> HGATP_MODE_SHIFT;
> > }
> > +
> > +int kvm_riscv_stage2_gpa_size(void)
> > +{
> > + return stage2_gpa_bits;
> > +}
>
> The ioctl & the underlying stage2_gpa_bits has bits.
> Maybe rename the function to kvm_riscv_stage2_gpa_bits as well ?
Okay, I will rename in the next revision.
Thanks,
Anup
>
> > diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c
> > index fb18af34a4b5..6f959639ec45 100644
> > --- a/arch/riscv/kvm/vm.c
> > +++ b/arch/riscv/kvm/vm.c
> > @@ -82,6 +82,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
> > case KVM_CAP_NR_MEMSLOTS:
> > r = KVM_USER_MEM_SLOTS;
> > break;
> > + case KVM_CAP_VM_GPA_BITS:
> > + r = kvm_riscv_stage2_gpa_size();
> > + break;
> > default:
> > r = 0;
> > break;
> > diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
> > index 1daa45268de2..469f05d69c8d 100644
> > --- a/include/uapi/linux/kvm.h
> > +++ b/include/uapi/linux/kvm.h
> > @@ -1131,6 +1131,7 @@ struct kvm_ppc_resize_hpt {
> > #define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204
> > #define KVM_CAP_ARM_MTE 205
> > #define KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM 206
> > +#define KVM_CAP_VM_GPA_BITS 207
> >
> > #ifdef KVM_CAP_IRQ_ROUTING
> >
> > --
> > 2.25.1
> >
>
> Other than that, it looks good to me.
>
> Reviewed-by: Atish Patra <atishp@rivosinc.com>
>
>
> --
> Regards,
> Atish
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA bits
@ 2021-12-17 6:08 ` Anup Patel
0 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-12-17 6:08 UTC (permalink / raw)
To: Atish Patra
Cc: Anup Patel, Paolo Bonzini, Shuah Khan, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Alistair Francis, KVM General,
kvm-riscv, linux-riscv, linux-kernel@vger.kernel.org List,
linux-kselftest
On Fri, Dec 17, 2021 at 11:17 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > The number of GPA bits supported for a RISC-V Guest/VM is based on the
> > MMU mode used by the G-stage translation. The KVM RISC-V will detect and
> > use the best possible MMU mode for the G-stage in kvm_arch_init().
> >
> > We add a generic VM capability KVM_CAP_VM_GPA_BITS which can be used by
> > the KVM userspace to get the number of GPA (guest physical address) bits
> > supported for a Guest/VM.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > arch/riscv/include/asm/kvm_host.h | 1 +
> > arch/riscv/kvm/mmu.c | 5 +++++
> > arch/riscv/kvm/vm.c | 3 +++
> > include/uapi/linux/kvm.h | 1 +
> > 4 files changed, 10 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> > index 37589b953bcb..ae5d238607fe 100644
> > --- a/arch/riscv/include/asm/kvm_host.h
> > +++ b/arch/riscv/include/asm/kvm_host.h
> > @@ -221,6 +221,7 @@ void kvm_riscv_stage2_free_pgd(struct kvm *kvm);
> > void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu);
> > void kvm_riscv_stage2_mode_detect(void);
> > unsigned long kvm_riscv_stage2_mode(void);
> > +int kvm_riscv_stage2_gpa_size(void);
> >
> > void kvm_riscv_stage2_vmid_detect(void);
> > unsigned long kvm_riscv_stage2_vmid_bits(void);
> > diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
> > index 9ffd0255af43..9b6d6465094f 100644
> > --- a/arch/riscv/kvm/mmu.c
> > +++ b/arch/riscv/kvm/mmu.c
> > @@ -760,3 +760,8 @@ unsigned long kvm_riscv_stage2_mode(void)
> > {
> > return stage2_mode >> HGATP_MODE_SHIFT;
> > }
> > +
> > +int kvm_riscv_stage2_gpa_size(void)
> > +{
> > + return stage2_gpa_bits;
> > +}
>
> The ioctl & the underlying stage2_gpa_bits has bits.
> Maybe rename the function to kvm_riscv_stage2_gpa_bits as well ?
Okay, I will rename in the next revision.
Thanks,
Anup
>
> > diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c
> > index fb18af34a4b5..6f959639ec45 100644
> > --- a/arch/riscv/kvm/vm.c
> > +++ b/arch/riscv/kvm/vm.c
> > @@ -82,6 +82,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
> > case KVM_CAP_NR_MEMSLOTS:
> > r = KVM_USER_MEM_SLOTS;
> > break;
> > + case KVM_CAP_VM_GPA_BITS:
> > + r = kvm_riscv_stage2_gpa_size();
> > + break;
> > default:
> > r = 0;
> > break;
> > diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
> > index 1daa45268de2..469f05d69c8d 100644
> > --- a/include/uapi/linux/kvm.h
> > +++ b/include/uapi/linux/kvm.h
> > @@ -1131,6 +1131,7 @@ struct kvm_ppc_resize_hpt {
> > #define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204
> > #define KVM_CAP_ARM_MTE 205
> > #define KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM 206
> > +#define KVM_CAP_VM_GPA_BITS 207
> >
> > #ifdef KVM_CAP_IRQ_ROUTING
> >
> > --
> > 2.25.1
> >
>
> Other than that, it looks good to me.
>
> Reviewed-by: Atish Patra <atishp@rivosinc.com>
>
>
> --
> Regards,
> Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA bits
2021-11-29 7:54 ` Anup Patel
@ 2021-12-17 8:28 ` Paolo Bonzini
-1 siblings, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2021-12-17 8:28 UTC (permalink / raw)
To: Anup Patel, Shuah Khan, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
linux-kselftest
On 11/29/21 08:54, Anup Patel wrote:
> The number of GPA bits supported for a RISC-V Guest/VM is based on the
> MMU mode used by the G-stage translation. The KVM RISC-V will detect and
> use the best possible MMU mode for the G-stage in kvm_arch_init().
>
> We add a generic VM capability KVM_CAP_VM_GPA_BITS which can be used by
> the KVM userspace to get the number of GPA (guest physical address) bits
> supported for a Guest/VM.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/kvm/mmu.c | 5 +++++
> arch/riscv/kvm/vm.c | 3 +++
> include/uapi/linux/kvm.h | 1 +
> 4 files changed, 10 insertions(+)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index 37589b953bcb..ae5d238607fe 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -221,6 +221,7 @@ void kvm_riscv_stage2_free_pgd(struct kvm *kvm);
> void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu);
> void kvm_riscv_stage2_mode_detect(void);
> unsigned long kvm_riscv_stage2_mode(void);
> +int kvm_riscv_stage2_gpa_size(void);
>
> void kvm_riscv_stage2_vmid_detect(void);
> unsigned long kvm_riscv_stage2_vmid_bits(void);
> diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
> index 9ffd0255af43..9b6d6465094f 100644
> --- a/arch/riscv/kvm/mmu.c
> +++ b/arch/riscv/kvm/mmu.c
> @@ -760,3 +760,8 @@ unsigned long kvm_riscv_stage2_mode(void)
> {
> return stage2_mode >> HGATP_MODE_SHIFT;
> }
> +
> +int kvm_riscv_stage2_gpa_size(void)
> +{
> + return stage2_gpa_bits;
> +}
> diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c
> index fb18af34a4b5..6f959639ec45 100644
> --- a/arch/riscv/kvm/vm.c
> +++ b/arch/riscv/kvm/vm.c
> @@ -82,6 +82,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
> case KVM_CAP_NR_MEMSLOTS:
> r = KVM_USER_MEM_SLOTS;
> break;
> + case KVM_CAP_VM_GPA_BITS:
> + r = kvm_riscv_stage2_gpa_size();
> + break;
> default:
> r = 0;
> break;
> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
> index 1daa45268de2..469f05d69c8d 100644
> --- a/include/uapi/linux/kvm.h
> +++ b/include/uapi/linux/kvm.h
> @@ -1131,6 +1131,7 @@ struct kvm_ppc_resize_hpt {
> #define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204
> #define KVM_CAP_ARM_MTE 205
> #define KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM 206
> +#define KVM_CAP_VM_GPA_BITS 207
>
> #ifdef KVM_CAP_IRQ_ROUTING
>
>
This is nice and other architectures could support it.
Paolo
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA bits
@ 2021-12-17 8:28 ` Paolo Bonzini
0 siblings, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2021-12-17 8:28 UTC (permalink / raw)
To: Anup Patel, Shuah Khan, Atish Patra
Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
Anup Patel, kvm, kvm-riscv, linux-riscv, linux-kernel,
linux-kselftest
On 11/29/21 08:54, Anup Patel wrote:
> The number of GPA bits supported for a RISC-V Guest/VM is based on the
> MMU mode used by the G-stage translation. The KVM RISC-V will detect and
> use the best possible MMU mode for the G-stage in kvm_arch_init().
>
> We add a generic VM capability KVM_CAP_VM_GPA_BITS which can be used by
> the KVM userspace to get the number of GPA (guest physical address) bits
> supported for a Guest/VM.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/kvm/mmu.c | 5 +++++
> arch/riscv/kvm/vm.c | 3 +++
> include/uapi/linux/kvm.h | 1 +
> 4 files changed, 10 insertions(+)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index 37589b953bcb..ae5d238607fe 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -221,6 +221,7 @@ void kvm_riscv_stage2_free_pgd(struct kvm *kvm);
> void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu);
> void kvm_riscv_stage2_mode_detect(void);
> unsigned long kvm_riscv_stage2_mode(void);
> +int kvm_riscv_stage2_gpa_size(void);
>
> void kvm_riscv_stage2_vmid_detect(void);
> unsigned long kvm_riscv_stage2_vmid_bits(void);
> diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
> index 9ffd0255af43..9b6d6465094f 100644
> --- a/arch/riscv/kvm/mmu.c
> +++ b/arch/riscv/kvm/mmu.c
> @@ -760,3 +760,8 @@ unsigned long kvm_riscv_stage2_mode(void)
> {
> return stage2_mode >> HGATP_MODE_SHIFT;
> }
> +
> +int kvm_riscv_stage2_gpa_size(void)
> +{
> + return stage2_gpa_bits;
> +}
> diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c
> index fb18af34a4b5..6f959639ec45 100644
> --- a/arch/riscv/kvm/vm.c
> +++ b/arch/riscv/kvm/vm.c
> @@ -82,6 +82,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
> case KVM_CAP_NR_MEMSLOTS:
> r = KVM_USER_MEM_SLOTS;
> break;
> + case KVM_CAP_VM_GPA_BITS:
> + r = kvm_riscv_stage2_gpa_size();
> + break;
> default:
> r = 0;
> break;
> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
> index 1daa45268de2..469f05d69c8d 100644
> --- a/include/uapi/linux/kvm.h
> +++ b/include/uapi/linux/kvm.h
> @@ -1131,6 +1131,7 @@ struct kvm_ppc_resize_hpt {
> #define KVM_CAP_EXIT_ON_EMULATION_FAILURE 204
> #define KVM_CAP_ARM_MTE 205
> #define KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM 206
> +#define KVM_CAP_VM_GPA_BITS 207
>
> #ifdef KVM_CAP_IRQ_ROUTING
>
>
This is nice and other architectures could support it.
Paolo
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 3/4] KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
2021-11-29 7:54 ` Anup Patel
@ 2021-12-20 19:45 ` Sean Christopherson
-1 siblings, 0 replies; 30+ messages in thread
From: Sean Christopherson @ 2021-12-20 19:45 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Shuah Khan, Atish Patra, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Alistair Francis, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, linux-kselftest
On Mon, Nov 29, 2021, Anup Patel wrote:
> We add EXTRA_CFLAGS to the common CFLAGS of top-level Makefile
Nit, wrap closer to 75 chars.
> which will allow users to pass additional compile-time flags such
> as "-static".
In case there's any hesitation in applying this (Paolo asked if this was just for
debugging in v1), being able to pass "-static" is helpful for our environment as
our test systems have a funky and minimal configuration (no gcc, and the interpreter
is in a weird location). Running selftests either requires building them with
-static or creating a symbolic link for /lib64/ld-linux-x86-64.so.2. It's generally
easier to just tell people to compile with -static.
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
Reviewed-and-tested-by: Sean Christopherson <seanjc@google.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 3/4] KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
@ 2021-12-20 19:45 ` Sean Christopherson
0 siblings, 0 replies; 30+ messages in thread
From: Sean Christopherson @ 2021-12-20 19:45 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Shuah Khan, Atish Patra, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Alistair Francis, Anup Patel, kvm,
kvm-riscv, linux-riscv, linux-kernel, linux-kselftest
On Mon, Nov 29, 2021, Anup Patel wrote:
> We add EXTRA_CFLAGS to the common CFLAGS of top-level Makefile
Nit, wrap closer to 75 chars.
> which will allow users to pass additional compile-time flags such
> as "-static".
In case there's any hesitation in applying this (Paolo asked if this was just for
debugging in v1), being able to pass "-static" is helpful for our environment as
our test systems have a funky and minimal configuration (no gcc, and the interpreter
is in a weird location). Running selftests either requires building them with
-static or creating a symbolic link for /lib64/ld-linux-x86-64.so.2. It's generally
easier to just tell people to compile with -static.
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
Reviewed-and-tested-by: Sean Christopherson <seanjc@google.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 3/4] KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
2021-12-20 19:45 ` Sean Christopherson
@ 2021-12-21 9:18 ` Anup Patel
-1 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-12-21 9:18 UTC (permalink / raw)
To: Sean Christopherson
Cc: Anup Patel, Paolo Bonzini, Shuah Khan, Atish Patra,
Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
KVM General, kvm-riscv, linux-riscv,
linux-kernel@vger.kernel.org List, linux-kselftest
On Tue, Dec 21, 2021 at 1:15 AM Sean Christopherson <seanjc@google.com> wrote:
>
> On Mon, Nov 29, 2021, Anup Patel wrote:
> > We add EXTRA_CFLAGS to the common CFLAGS of top-level Makefile
>
> Nit, wrap closer to 75 chars.
Okay, I will update.
>
> > which will allow users to pass additional compile-time flags such
> > as "-static".
>
> In case there's any hesitation in applying this (Paolo asked if this was just for
> debugging in v1), being able to pass "-static" is helpful for our environment as
> our test systems have a funky and minimal configuration (no gcc, and the interpreter
> is in a weird location). Running selftests either requires building them with
> -static or creating a symbolic link for /lib64/ld-linux-x86-64.so.2. It's generally
> easier to just tell people to compile with -static.
>
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
>
> Reviewed-and-tested-by: Sean Christopherson <seanjc@google.com>
Thanks, I am planning to queue this for 5.17. Currently, I am waiting for
some reviews on the PATCH4 (last patch).
Regards,
Anup
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 3/4] KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
@ 2021-12-21 9:18 ` Anup Patel
0 siblings, 0 replies; 30+ messages in thread
From: Anup Patel @ 2021-12-21 9:18 UTC (permalink / raw)
To: Sean Christopherson
Cc: Anup Patel, Paolo Bonzini, Shuah Khan, Atish Patra,
Palmer Dabbelt, Paul Walmsley, Albert Ou, Alistair Francis,
KVM General, kvm-riscv, linux-riscv,
linux-kernel@vger.kernel.org List, linux-kselftest
On Tue, Dec 21, 2021 at 1:15 AM Sean Christopherson <seanjc@google.com> wrote:
>
> On Mon, Nov 29, 2021, Anup Patel wrote:
> > We add EXTRA_CFLAGS to the common CFLAGS of top-level Makefile
>
> Nit, wrap closer to 75 chars.
Okay, I will update.
>
> > which will allow users to pass additional compile-time flags such
> > as "-static".
>
> In case there's any hesitation in applying this (Paolo asked if this was just for
> debugging in v1), being able to pass "-static" is helpful for our environment as
> our test systems have a funky and minimal configuration (no gcc, and the interpreter
> is in a weird location). Running selftests either requires building them with
> -static or creating a symbolic link for /lib64/ld-linux-x86-64.so.2. It's generally
> easier to just tell people to compile with -static.
>
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
>
> Reviewed-and-tested-by: Sean Christopherson <seanjc@google.com>
Thanks, I am planning to queue this for 5.17. Currently, I am waiting for
some reviews on the PATCH4 (last patch).
Regards,
Anup
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 4/4] KVM: selftests: Add initial support for RISC-V 64-bit
2021-11-29 7:54 ` Anup Patel
@ 2021-12-22 8:48 ` Atish Patra
-1 siblings, 0 replies; 30+ messages in thread
From: Atish Patra @ 2021-12-22 8:48 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Shuah Khan, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Alistair Francis, Anup Patel, KVM General, kvm-riscv,
linux-riscv, linux-kernel@vger.kernel.org List, linux-kselftest
On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> We add initial support for RISC-V 64-bit in KVM selftests using
> which we can cross-compile and run arch independent tests such as:
> demand_paging_test
> dirty_log_test
> kvm_create_max_vcpus,
> kvm_page_table_test
> set_memory_region_test
> kvm_binary_stats_test
>
> All VM guest modes defined in kvm_util.h require at least 48-bit
> guest virtual address so to use KVM RISC-V selftests hardware
> need to support at least Sv48 MMU for guest (i.e. VS-mode).
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> tools/testing/selftests/kvm/Makefile | 12 +
> .../testing/selftests/kvm/include/kvm_util.h | 10 +
> .../selftests/kvm/include/riscv/processor.h | 135 +++++++
> tools/testing/selftests/kvm/lib/guest_modes.c | 10 +
> .../selftests/kvm/lib/riscv/processor.c | 362 ++++++++++++++++++
> tools/testing/selftests/kvm/lib/riscv/ucall.c | 87 +++++
> 6 files changed, 616 insertions(+)
> create mode 100644 tools/testing/selftests/kvm/include/riscv/processor.h
> create mode 100644 tools/testing/selftests/kvm/lib/riscv/processor.c
> create mode 100644 tools/testing/selftests/kvm/lib/riscv/ucall.c
>
> diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
> index ee6740e9ecdb..2d825d1e7ff2 100644
> --- a/tools/testing/selftests/kvm/Makefile
> +++ b/tools/testing/selftests/kvm/Makefile
> @@ -32,11 +32,16 @@ endif
> ifeq ($(ARCH),s390)
> UNAME_M := s390x
> endif
> +# Set UNAME_M riscv compile/install to work
> +ifeq ($(ARCH),riscv)
> + UNAME_M := riscv
> +endif
>
> LIBKVM = lib/assert.c lib/elf.c lib/io.c lib/kvm_util.c lib/rbtree.c lib/sparsebit.c lib/test_util.c lib/guest_modes.c lib/perf_test_util.c
> LIBKVM_x86_64 = lib/x86_64/apic.c lib/x86_64/processor.c lib/x86_64/vmx.c lib/x86_64/svm.c lib/x86_64/ucall.c lib/x86_64/handlers.S
> LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S lib/aarch64/spinlock.c lib/aarch64/gic.c lib/aarch64/gic_v3.c lib/aarch64/vgic.c
> LIBKVM_s390x = lib/s390x/processor.c lib/s390x/ucall.c lib/s390x/diag318_test_handler.c
> +LIBKVM_riscv = lib/riscv/processor.c lib/riscv/ucall.c
>
> TEST_GEN_PROGS_x86_64 = x86_64/cr4_cpuid_sync_test
> TEST_GEN_PROGS_x86_64 += x86_64/get_msr_index_features
> @@ -117,6 +122,13 @@ TEST_GEN_PROGS_s390x += rseq_test
> TEST_GEN_PROGS_s390x += set_memory_region_test
> TEST_GEN_PROGS_s390x += kvm_binary_stats_test
>
> +TEST_GEN_PROGS_riscv += demand_paging_test
> +TEST_GEN_PROGS_riscv += dirty_log_test
> +TEST_GEN_PROGS_riscv += kvm_create_max_vcpus
> +TEST_GEN_PROGS_riscv += kvm_page_table_test
> +TEST_GEN_PROGS_riscv += set_memory_region_test
> +TEST_GEN_PROGS_riscv += kvm_binary_stats_test
> +
> TEST_GEN_PROGS += $(TEST_GEN_PROGS_$(UNAME_M))
> LIBKVM += $(LIBKVM_$(UNAME_M))
>
> diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h
> index 6a1a37f30494..c23e5be14862 100644
> --- a/tools/testing/selftests/kvm/include/kvm_util.h
> +++ b/tools/testing/selftests/kvm/include/kvm_util.h
> @@ -69,6 +69,16 @@ enum vm_guest_mode {
> #define MIN_PAGE_SHIFT 12U
> #define ptes_per_page(page_size) ((page_size) / 16)
>
> +#elif defined(__riscv)
> +
> +#if __riscv_xlen == 32
> +#error "RISC-V 32-bit kvm selftests not supported"
> +#endif
> +
> +#define VM_MODE_DEFAULT VM_MODE_P40V48_4K
> +#define MIN_PAGE_SHIFT 12U
> +#define ptes_per_page(page_size) ((page_size) / 8)
> +
> #endif
>
> #define MIN_PAGE_SIZE (1U << MIN_PAGE_SHIFT)
> diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
> new file mode 100644
> index 000000000000..dc284c6bdbc3
> --- /dev/null
> +++ b/tools/testing/selftests/kvm/include/riscv/processor.h
> @@ -0,0 +1,135 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * RISC-V processor specific defines
> + *
> + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> + */
> +#ifndef SELFTEST_KVM_PROCESSOR_H
> +#define SELFTEST_KVM_PROCESSOR_H
> +
> +#include "kvm_util.h"
> +#include <linux/stringify.h>
> +
> +static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx,
> + uint64_t size)
> +{
> + return KVM_REG_RISCV | type | idx | size;
> +}
> +
> +#if __riscv_xlen == 64
> +#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64
> +#else
> +#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32
> +#endif
> +
> +#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, \
> + KVM_REG_RISCV_CONFIG_REG(name), \
> + KVM_REG_SIZE_ULONG)
> +
> +#define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, \
> + KVM_REG_RISCV_CORE_REG(name), \
> + KVM_REG_SIZE_ULONG)
> +
> +#define RISCV_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \
> + KVM_REG_RISCV_CSR_REG(name), \
> + KVM_REG_SIZE_ULONG)
> +
> +#define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, \
> + KVM_REG_RISCV_TIMER_REG(name), \
> + KVM_REG_SIZE_U64)
> +
> +static inline void get_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
> + unsigned long *addr)
> +{
> + struct kvm_one_reg reg;
> +
> + reg.id = id;
> + reg.addr = (unsigned long)addr;
> + vcpu_get_reg(vm, vcpuid, ®);
> +}
> +
> +static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
> + unsigned long val)
> +{
> + struct kvm_one_reg reg;
> +
> + reg.id = id;
> + reg.addr = (unsigned long)&val;
> + vcpu_set_reg(vm, vcpuid, ®);
> +}
> +
> +/* L3 index Bit[47:39] */
> +#define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL
> +#define PGTBL_L3_INDEX_SHIFT 39
> +#define PGTBL_L3_BLOCK_SHIFT 39
> +#define PGTBL_L3_BLOCK_SIZE 0x0000008000000000ULL
> +#define PGTBL_L3_MAP_MASK (~(PGTBL_L3_BLOCK_SIZE - 1))
> +/* L2 index Bit[38:30] */
> +#define PGTBL_L2_INDEX_MASK 0x0000007FC0000000ULL
> +#define PGTBL_L2_INDEX_SHIFT 30
> +#define PGTBL_L2_BLOCK_SHIFT 30
> +#define PGTBL_L2_BLOCK_SIZE 0x0000000040000000ULL
> +#define PGTBL_L2_MAP_MASK (~(PGTBL_L2_BLOCK_SIZE - 1))
> +/* L1 index Bit[29:21] */
> +#define PGTBL_L1_INDEX_MASK 0x000000003FE00000ULL
> +#define PGTBL_L1_INDEX_SHIFT 21
> +#define PGTBL_L1_BLOCK_SHIFT 21
> +#define PGTBL_L1_BLOCK_SIZE 0x0000000000200000ULL
> +#define PGTBL_L1_MAP_MASK (~(PGTBL_L1_BLOCK_SIZE - 1))
> +/* L0 index Bit[20:12] */
> +#define PGTBL_L0_INDEX_MASK 0x00000000001FF000ULL
> +#define PGTBL_L0_INDEX_SHIFT 12
> +#define PGTBL_L0_BLOCK_SHIFT 12
> +#define PGTBL_L0_BLOCK_SIZE 0x0000000000001000ULL
> +#define PGTBL_L0_MAP_MASK (~(PGTBL_L0_BLOCK_SIZE - 1))
> +
> +#define PGTBL_PTE_ADDR_MASK 0x003FFFFFFFFFFC00ULL
> +#define PGTBL_PTE_ADDR_SHIFT 10
> +#define PGTBL_PTE_RSW_MASK 0x0000000000000300ULL
> +#define PGTBL_PTE_RSW_SHIFT 8
> +#define PGTBL_PTE_DIRTY_MASK 0x0000000000000080ULL
> +#define PGTBL_PTE_DIRTY_SHIFT 7
> +#define PGTBL_PTE_ACCESSED_MASK 0x0000000000000040ULL
> +#define PGTBL_PTE_ACCESSED_SHIFT 6
> +#define PGTBL_PTE_GLOBAL_MASK 0x0000000000000020ULL
> +#define PGTBL_PTE_GLOBAL_SHIFT 5
> +#define PGTBL_PTE_USER_MASK 0x0000000000000010ULL
> +#define PGTBL_PTE_USER_SHIFT 4
> +#define PGTBL_PTE_EXECUTE_MASK 0x0000000000000008ULL
> +#define PGTBL_PTE_EXECUTE_SHIFT 3
> +#define PGTBL_PTE_WRITE_MASK 0x0000000000000004ULL
> +#define PGTBL_PTE_WRITE_SHIFT 2
> +#define PGTBL_PTE_READ_MASK 0x0000000000000002ULL
> +#define PGTBL_PTE_READ_SHIFT 1
> +#define PGTBL_PTE_PERM_MASK (PGTBL_PTE_EXECUTE_MASK | \
> + PGTBL_PTE_WRITE_MASK | \
> + PGTBL_PTE_READ_MASK)
> +#define PGTBL_PTE_VALID_MASK 0x0000000000000001ULL
> +#define PGTBL_PTE_VALID_SHIFT 0
> +
> +#define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE
> +#define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT
> +
> +#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
> +#define SATP_MODE_39 _AC(0x8000000000000000, UL)
> +#define SATP_MODE_48 _AC(0x9000000000000000, UL)
> +#define SATP_ASID_BITS 16
> +#define SATP_ASID_SHIFT 44
> +#define SATP_ASID_MASK _AC(0xFFFF, UL)
> +
> +#define SBI_EXT_EXPERIMENTAL_START 0x08000000
> +#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF
> +
> +#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END
> +
> +struct sbiret {
> + long error;
> + long value;
> +};
> +
> +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> + unsigned long arg1, unsigned long arg2,
> + unsigned long arg3, unsigned long arg4,
> + unsigned long arg5);
> +
> +#endif /* SELFTEST_KVM_PROCESSOR_H */
> diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/selftests/kvm/lib/guest_modes.c
> index c330f414ef96..57839a12e472 100644
> --- a/tools/testing/selftests/kvm/lib/guest_modes.c
> +++ b/tools/testing/selftests/kvm/lib/guest_modes.c
> @@ -38,6 +38,16 @@ void guest_modes_append_default(void)
> guest_mode_append(VM_MODE_P47V64_4K, true, true);
> }
> #endif
> +#ifdef __riscv
> + {
> + unsigned int sz = kvm_check_cap(KVM_CAP_VM_GPA_BITS);
> +
> + if (sz >= 52)
> + guest_mode_append(VM_MODE_P52V48_4K, true, true);
> + if (sz >= 48)
> + guest_mode_append(VM_MODE_P48V48_4K, true, true);
> + }
> +#endif
> }
>
> void for_each_guest_mode(void (*func)(enum vm_guest_mode, void *), void *arg)
> diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
> new file mode 100644
> index 000000000000..d377f2603d98
> --- /dev/null
> +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
> @@ -0,0 +1,362 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * RISC-V code
> + *
> + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> + */
> +
> +#include <linux/compiler.h>
> +#include <assert.h>
> +
> +#include "kvm_util.h"
> +#include "../kvm_util_internal.h"
> +#include "processor.h"
> +
> +#define DEFAULT_RISCV_GUEST_STACK_VADDR_MIN 0xac0000
> +
> +static uint64_t page_align(struct kvm_vm *vm, uint64_t v)
> +{
> + return (v + vm->page_size) & ~(vm->page_size - 1);
> +}
> +
> +static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry)
> +{
> + return ((entry & PGTBL_PTE_ADDR_MASK) >> PGTBL_PTE_ADDR_SHIFT) <<
> + PGTBL_PAGE_SIZE_SHIFT;
> +}
> +
> +static uint64_t ptrs_per_pte(struct kvm_vm *vm)
> +{
> + return PGTBL_PAGE_SIZE / sizeof(uint64_t);
> +}
> +
> +static uint64_t pte_index_mask[] = {
> + PGTBL_L0_INDEX_MASK,
> + PGTBL_L1_INDEX_MASK,
> + PGTBL_L2_INDEX_MASK,
> + PGTBL_L3_INDEX_MASK,
> +};
> +
> +static uint32_t pte_index_shift[] = {
> + PGTBL_L0_INDEX_SHIFT,
> + PGTBL_L1_INDEX_SHIFT,
> + PGTBL_L2_INDEX_SHIFT,
> + PGTBL_L3_INDEX_SHIFT,
> +};
> +
> +static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level)
> +{
> + TEST_ASSERT(level > -1,
> + "Negative page table level (%d) not possible", level);
> + TEST_ASSERT(level < vm->pgtable_levels,
> + "Invalid page table level (%d)", level);
> +
> + return (gva & pte_index_mask[level]) >> pte_index_shift[level];
> +}
> +
> +void virt_pgd_alloc(struct kvm_vm *vm)
> +{
> + if (!vm->pgd_created) {
> + vm_paddr_t paddr = vm_phy_pages_alloc(vm,
> + page_align(vm, ptrs_per_pte(vm) * 8) / vm->page_size,
> + KVM_GUEST_PAGE_TABLE_MIN_PADDR, 0);
> + vm->pgd = paddr;
> + vm->pgd_created = true;
> + }
> +}
> +
> +void virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
> +{
> + uint64_t *ptep, next_ppn;
> + int level = vm->pgtable_levels - 1;
> +
> + TEST_ASSERT((vaddr % vm->page_size) == 0,
> + "Virtual address not on page boundary,\n"
> + " vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size);
> + TEST_ASSERT(sparsebit_is_set(vm->vpages_valid,
> + (vaddr >> vm->page_shift)),
> + "Invalid virtual address, vaddr: 0x%lx", vaddr);
> + TEST_ASSERT((paddr % vm->page_size) == 0,
> + "Physical address not on page boundary,\n"
> + " paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size);
> + TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
> + "Physical address beyond maximum supported,\n"
> + " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
> + paddr, vm->max_gfn, vm->page_size);
> +
> + ptep = addr_gpa2hva(vm, vm->pgd) + pte_index(vm, vaddr, level) * 8;
> + if (!*ptep) {
> + next_ppn = vm_alloc_page_table(vm) >> PGTBL_PAGE_SIZE_SHIFT;
> + *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) |
> + PGTBL_PTE_VALID_MASK;
> + }
> + level--;
> +
> + while (level > -1) {
> + ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) +
> + pte_index(vm, vaddr, level) * 8;
> + if (!*ptep && level > 0) {
> + next_ppn = vm_alloc_page_table(vm) >>
> + PGTBL_PAGE_SIZE_SHIFT;
> + *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) |
> + PGTBL_PTE_VALID_MASK;
> + }
> + level--;
> + }
> +
> + paddr = paddr >> PGTBL_PAGE_SIZE_SHIFT;
> + *ptep = (paddr << PGTBL_PTE_ADDR_SHIFT) |
> + PGTBL_PTE_PERM_MASK | PGTBL_PTE_VALID_MASK;
> +}
> +
> +vm_paddr_t addr_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
> +{
> + uint64_t *ptep;
> + int level = vm->pgtable_levels - 1;
> +
> + if (!vm->pgd_created)
> + goto unmapped_gva;
> +
> + ptep = addr_gpa2hva(vm, vm->pgd) + pte_index(vm, gva, level) * 8;
> + if (!ptep)
> + goto unmapped_gva;
> + level--;
> +
> + while (level > -1) {
> + ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) +
> + pte_index(vm, gva, level) * 8;
> + if (!ptep)
> + goto unmapped_gva;
> + level--;
> + }
> +
> + return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1));
> +
> +unmapped_gva:
> + TEST_FAIL("No mapping for vm virtual address gva: 0x%lx level: %d",
> + gva, level);
> + exit(1);
> +}
> +
> +static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent,
> + uint64_t page, int level)
> +{
> +#ifdef DEBUG
> + static const char *const type[] = { "pte", "pmd", "pud", "p4d"};
> + uint64_t pte, *ptep;
> +
> + if (level < 0)
> + return;
> +
> + for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) {
> + ptep = addr_gpa2hva(vm, pte);
> + if (!*ptep)
> + continue;
> + fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "",
> + type[level], pte, *ptep, ptep);
> + pte_dump(stream, vm, indent + 1,
> + pte_addr(vm, *ptep), level - 1);
> + }
> +#endif
> +}
> +
> +void virt_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
> +{
> + int level = vm->pgtable_levels - 1;
> + uint64_t pgd, *ptep;
> +
> + if (!vm->pgd_created)
> + return;
> +
> + for (pgd = vm->pgd; pgd < vm->pgd + ptrs_per_pte(vm) * 8; pgd += 8) {
> + ptep = addr_gpa2hva(vm, pgd);
> + if (!*ptep)
> + continue;
> + fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "",
> + pgd, *ptep, ptep);
> + pte_dump(stream, vm, indent + 1,
> + pte_addr(vm, *ptep), level - 1);
> + }
> +}
> +
> +void riscv_vcpu_mmu_setup(struct kvm_vm *vm, int vcpuid)
> +{
> + unsigned long satp;
> +
> + /*
> + * The RISC-V Sv48 MMU mode supports 56-bit physical address
> + * for 48-bit virtual address with 4KB last level page size.
> + */
> + switch (vm->mode) {
> + case VM_MODE_P52V48_4K:
> + case VM_MODE_P48V48_4K:
> + case VM_MODE_P40V48_4K:
> + break;
> + default:
> + TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode);
> + }
> +
> + satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN;
> + satp |= SATP_MODE_48;
> +
> + set_reg(vm, vcpuid, RISCV_CSR_REG(satp), satp);
> +}
> +
> +void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint8_t indent)
> +{
> + struct kvm_riscv_core core;
> +
> + get_reg(vm, vcpuid, RISCV_CORE_REG(mode), &core.mode);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.pc), &core.regs.pc);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.ra), &core.regs.ra);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.sp), &core.regs.sp);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.gp), &core.regs.gp);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.tp), &core.regs.tp);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t0), &core.regs.t0);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t1), &core.regs.t1);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t2), &core.regs.t2);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s0), &core.regs.s0);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s1), &core.regs.s1);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a0), &core.regs.a0);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a1), &core.regs.a1);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a2), &core.regs.a2);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a3), &core.regs.a3);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a4), &core.regs.a4);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a5), &core.regs.a5);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a6), &core.regs.a6);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a7), &core.regs.a7);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s2), &core.regs.s2);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s3), &core.regs.s3);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s4), &core.regs.s4);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s5), &core.regs.s5);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s6), &core.regs.s6);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s7), &core.regs.s7);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s8), &core.regs.s8);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s9), &core.regs.s9);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s10), &core.regs.s10);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s11), &core.regs.s11);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t3), &core.regs.t3);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t4), &core.regs.t4);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t5), &core.regs.t5);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t6), &core.regs.t6);
> +
> + fprintf(stream,
> + " MODE: 0x%lx\n", core.mode);
> + fprintf(stream,
> + " PC: 0x%016lx RA: 0x%016lx SP: 0x%016lx GP: 0x%016lx\n",
> + core.regs.pc, core.regs.ra, core.regs.sp, core.regs.gp);
> + fprintf(stream,
> + " TP: 0x%016lx T0: 0x%016lx T1: 0x%016lx T2: 0x%016lx\n",
> + core.regs.tp, core.regs.t0, core.regs.t1, core.regs.t2);
> + fprintf(stream,
> + " S0: 0x%016lx S1: 0x%016lx A0: 0x%016lx A1: 0x%016lx\n",
> + core.regs.s0, core.regs.s1, core.regs.a0, core.regs.a1);
> + fprintf(stream,
> + " A2: 0x%016lx A3: 0x%016lx A4: 0x%016lx A5: 0x%016lx\n",
> + core.regs.a2, core.regs.a3, core.regs.a4, core.regs.a5);
> + fprintf(stream,
> + " A6: 0x%016lx A7: 0x%016lx S2: 0x%016lx S3: 0x%016lx\n",
> + core.regs.a6, core.regs.a7, core.regs.s2, core.regs.s3);
> + fprintf(stream,
> + " S4: 0x%016lx S5: 0x%016lx S6: 0x%016lx S7: 0x%016lx\n",
> + core.regs.s4, core.regs.s5, core.regs.s6, core.regs.s7);
> + fprintf(stream,
> + " S8: 0x%016lx S9: 0x%016lx S10: 0x%016lx S11: 0x%016lx\n",
> + core.regs.s8, core.regs.s9, core.regs.s10, core.regs.s11);
> + fprintf(stream,
> + " T3: 0x%016lx T4: 0x%016lx T5: 0x%016lx T6: 0x%016lx\n",
> + core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6);
> +}
> +
> +static void guest_hang(void)
> +{
> + while (1)
> + ;
> +}
> +
> +void vm_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, void *guest_code)
> +{
> + int r;
> + size_t stack_size = vm->page_size == 4096 ?
> + DEFAULT_STACK_PGS * vm->page_size :
> + vm->page_size;
> + unsigned long stack_vaddr = vm_vaddr_alloc(vm, stack_size,
> + DEFAULT_RISCV_GUEST_STACK_VADDR_MIN);
> + unsigned long current_gp = 0;
> + struct kvm_mp_state mps;
> +
> + vm_vcpu_add(vm, vcpuid);
> + riscv_vcpu_mmu_setup(vm, vcpuid);
> +
> + /*
> + * With SBI HSM support in KVM RISC-V, all secondary VCPUs are
> + * powered-off by default so we ensure that all secondary VCPUs
> + * are powered-on using KVM_SET_MP_STATE ioctl().
> + */
> + mps.mp_state = KVM_MP_STATE_RUNNABLE;
> + r = _vcpu_ioctl(vm, vcpuid, KVM_SET_MP_STATE, &mps);
> + TEST_ASSERT(!r, "IOCTL KVM_SET_MP_STATE failed (error %d)", r);
> +
> + /* Setup global pointer of guest to be same as the host */
> + asm volatile (
> + "add %0, gp, zero" : "=r" (current_gp) : : "memory");
> + set_reg(vm, vcpuid, RISCV_CORE_REG(regs.gp), current_gp);
> +
> + /* Setup stack pointer and program counter of guest */
> + set_reg(vm, vcpuid, RISCV_CORE_REG(regs.sp),
> + stack_vaddr + stack_size);
> + set_reg(vm, vcpuid, RISCV_CORE_REG(regs.pc),
> + (unsigned long)guest_code);
> +
> + /* Setup default exception vector of guest */
> + set_reg(vm, vcpuid, RISCV_CSR_REG(stvec),
> + (unsigned long)guest_hang);
> +}
> +
> +void vcpu_args_set(struct kvm_vm *vm, uint32_t vcpuid, unsigned int num, ...)
> +{
> + va_list ap;
> + uint64_t id = RISCV_CORE_REG(regs.a0);
> + int i;
> +
> + TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n"
> + " num: %u\n", num);
> +
> + va_start(ap, num);
> +
> + for (i = 0; i < num; i++) {
> + switch (i) {
> + case 0:
> + id = RISCV_CORE_REG(regs.a0);
> + break;
> + case 1:
> + id = RISCV_CORE_REG(regs.a1);
> + break;
> + case 2:
> + id = RISCV_CORE_REG(regs.a2);
> + break;
> + case 3:
> + id = RISCV_CORE_REG(regs.a3);
> + break;
> + case 4:
> + id = RISCV_CORE_REG(regs.a4);
> + break;
> + case 5:
> + id = RISCV_CORE_REG(regs.a5);
> + break;
> + case 6:
> + id = RISCV_CORE_REG(regs.a6);
> + break;
> + case 7:
> + id = RISCV_CORE_REG(regs.a7);
> + break;
> + };
> + set_reg(vm, vcpuid, id, va_arg(ap, uint64_t));
> + }
> +
> + va_end(ap);
> +}
> +
> +void assert_on_unhandled_exception(struct kvm_vm *vm, uint32_t vcpuid)
> +{
> +}
> diff --git a/tools/testing/selftests/kvm/lib/riscv/ucall.c b/tools/testing/selftests/kvm/lib/riscv/ucall.c
> new file mode 100644
> index 000000000000..9e42d8248fa6
> --- /dev/null
> +++ b/tools/testing/selftests/kvm/lib/riscv/ucall.c
> @@ -0,0 +1,87 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * ucall support. A ucall is a "hypercall to userspace".
> + *
> + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> + */
> +
> +#include <linux/kvm.h>
> +
> +#include "kvm_util.h"
> +#include "../kvm_util_internal.h"
> +#include "processor.h"
> +
> +void ucall_init(struct kvm_vm *vm, void *arg)
> +{
> +}
> +
> +void ucall_uninit(struct kvm_vm *vm)
> +{
> +}
> +
> +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> + unsigned long arg1, unsigned long arg2,
> + unsigned long arg3, unsigned long arg4,
> + unsigned long arg5)
> +{
> + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
> + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
> + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
> + register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
> + register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
> + register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
> + register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
> + register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
> + struct sbiret ret;
> +
> + asm volatile (
> + "ecall"
> + : "+r" (a0), "+r" (a1)
> + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
> + : "memory");
> + ret.error = a0;
> + ret.value = a1;
> +
> + return ret;
> +}
> +
> +void ucall(uint64_t cmd, int nargs, ...)
> +{
> + struct ucall uc = {
> + .cmd = cmd,
> + };
> + va_list va;
> + int i;
> +
> + nargs = nargs <= UCALL_MAX_ARGS ? nargs : UCALL_MAX_ARGS;
> +
> + va_start(va, nargs);
> + for (i = 0; i < nargs; ++i)
> + uc.args[i] = va_arg(va, uint64_t);
> + va_end(va);
> +
> + sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT, 0, (vm_vaddr_t)&uc,
> + 0, 0, 0, 0, 0);
> +}
> +
> +uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id, struct ucall *uc)
> +{
> + struct kvm_run *run = vcpu_state(vm, vcpu_id);
> + struct ucall ucall = {};
> +
> + if (uc)
> + memset(uc, 0, sizeof(*uc));
> +
> + if (run->exit_reason == KVM_EXIT_RISCV_SBI &&
> + run->riscv_sbi.extension_id == KVM_RISCV_SELFTESTS_SBI_EXT &&
> + run->riscv_sbi.function_id == 0) {
> + memcpy(&ucall, addr_gva2hva(vm, run->riscv_sbi.args[0]),
> + sizeof(ucall));
> +
> + vcpu_run_complete_io(vm, vcpu_id);
> + if (uc)
> + memcpy(uc, &ucall, sizeof(ucall));
> + }
> +
> + return ucall.cmd;
> +}
> --
> 2.25.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 4/4] KVM: selftests: Add initial support for RISC-V 64-bit
@ 2021-12-22 8:48 ` Atish Patra
0 siblings, 0 replies; 30+ messages in thread
From: Atish Patra @ 2021-12-22 8:48 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Shuah Khan, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Alistair Francis, Anup Patel, KVM General, kvm-riscv,
linux-riscv, linux-kernel@vger.kernel.org List, linux-kselftest
On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> We add initial support for RISC-V 64-bit in KVM selftests using
> which we can cross-compile and run arch independent tests such as:
> demand_paging_test
> dirty_log_test
> kvm_create_max_vcpus,
> kvm_page_table_test
> set_memory_region_test
> kvm_binary_stats_test
>
> All VM guest modes defined in kvm_util.h require at least 48-bit
> guest virtual address so to use KVM RISC-V selftests hardware
> need to support at least Sv48 MMU for guest (i.e. VS-mode).
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> tools/testing/selftests/kvm/Makefile | 12 +
> .../testing/selftests/kvm/include/kvm_util.h | 10 +
> .../selftests/kvm/include/riscv/processor.h | 135 +++++++
> tools/testing/selftests/kvm/lib/guest_modes.c | 10 +
> .../selftests/kvm/lib/riscv/processor.c | 362 ++++++++++++++++++
> tools/testing/selftests/kvm/lib/riscv/ucall.c | 87 +++++
> 6 files changed, 616 insertions(+)
> create mode 100644 tools/testing/selftests/kvm/include/riscv/processor.h
> create mode 100644 tools/testing/selftests/kvm/lib/riscv/processor.c
> create mode 100644 tools/testing/selftests/kvm/lib/riscv/ucall.c
>
> diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile
> index ee6740e9ecdb..2d825d1e7ff2 100644
> --- a/tools/testing/selftests/kvm/Makefile
> +++ b/tools/testing/selftests/kvm/Makefile
> @@ -32,11 +32,16 @@ endif
> ifeq ($(ARCH),s390)
> UNAME_M := s390x
> endif
> +# Set UNAME_M riscv compile/install to work
> +ifeq ($(ARCH),riscv)
> + UNAME_M := riscv
> +endif
>
> LIBKVM = lib/assert.c lib/elf.c lib/io.c lib/kvm_util.c lib/rbtree.c lib/sparsebit.c lib/test_util.c lib/guest_modes.c lib/perf_test_util.c
> LIBKVM_x86_64 = lib/x86_64/apic.c lib/x86_64/processor.c lib/x86_64/vmx.c lib/x86_64/svm.c lib/x86_64/ucall.c lib/x86_64/handlers.S
> LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S lib/aarch64/spinlock.c lib/aarch64/gic.c lib/aarch64/gic_v3.c lib/aarch64/vgic.c
> LIBKVM_s390x = lib/s390x/processor.c lib/s390x/ucall.c lib/s390x/diag318_test_handler.c
> +LIBKVM_riscv = lib/riscv/processor.c lib/riscv/ucall.c
>
> TEST_GEN_PROGS_x86_64 = x86_64/cr4_cpuid_sync_test
> TEST_GEN_PROGS_x86_64 += x86_64/get_msr_index_features
> @@ -117,6 +122,13 @@ TEST_GEN_PROGS_s390x += rseq_test
> TEST_GEN_PROGS_s390x += set_memory_region_test
> TEST_GEN_PROGS_s390x += kvm_binary_stats_test
>
> +TEST_GEN_PROGS_riscv += demand_paging_test
> +TEST_GEN_PROGS_riscv += dirty_log_test
> +TEST_GEN_PROGS_riscv += kvm_create_max_vcpus
> +TEST_GEN_PROGS_riscv += kvm_page_table_test
> +TEST_GEN_PROGS_riscv += set_memory_region_test
> +TEST_GEN_PROGS_riscv += kvm_binary_stats_test
> +
> TEST_GEN_PROGS += $(TEST_GEN_PROGS_$(UNAME_M))
> LIBKVM += $(LIBKVM_$(UNAME_M))
>
> diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h
> index 6a1a37f30494..c23e5be14862 100644
> --- a/tools/testing/selftests/kvm/include/kvm_util.h
> +++ b/tools/testing/selftests/kvm/include/kvm_util.h
> @@ -69,6 +69,16 @@ enum vm_guest_mode {
> #define MIN_PAGE_SHIFT 12U
> #define ptes_per_page(page_size) ((page_size) / 16)
>
> +#elif defined(__riscv)
> +
> +#if __riscv_xlen == 32
> +#error "RISC-V 32-bit kvm selftests not supported"
> +#endif
> +
> +#define VM_MODE_DEFAULT VM_MODE_P40V48_4K
> +#define MIN_PAGE_SHIFT 12U
> +#define ptes_per_page(page_size) ((page_size) / 8)
> +
> #endif
>
> #define MIN_PAGE_SIZE (1U << MIN_PAGE_SHIFT)
> diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
> new file mode 100644
> index 000000000000..dc284c6bdbc3
> --- /dev/null
> +++ b/tools/testing/selftests/kvm/include/riscv/processor.h
> @@ -0,0 +1,135 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * RISC-V processor specific defines
> + *
> + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> + */
> +#ifndef SELFTEST_KVM_PROCESSOR_H
> +#define SELFTEST_KVM_PROCESSOR_H
> +
> +#include "kvm_util.h"
> +#include <linux/stringify.h>
> +
> +static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx,
> + uint64_t size)
> +{
> + return KVM_REG_RISCV | type | idx | size;
> +}
> +
> +#if __riscv_xlen == 64
> +#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64
> +#else
> +#define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32
> +#endif
> +
> +#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, \
> + KVM_REG_RISCV_CONFIG_REG(name), \
> + KVM_REG_SIZE_ULONG)
> +
> +#define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, \
> + KVM_REG_RISCV_CORE_REG(name), \
> + KVM_REG_SIZE_ULONG)
> +
> +#define RISCV_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \
> + KVM_REG_RISCV_CSR_REG(name), \
> + KVM_REG_SIZE_ULONG)
> +
> +#define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, \
> + KVM_REG_RISCV_TIMER_REG(name), \
> + KVM_REG_SIZE_U64)
> +
> +static inline void get_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
> + unsigned long *addr)
> +{
> + struct kvm_one_reg reg;
> +
> + reg.id = id;
> + reg.addr = (unsigned long)addr;
> + vcpu_get_reg(vm, vcpuid, ®);
> +}
> +
> +static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id,
> + unsigned long val)
> +{
> + struct kvm_one_reg reg;
> +
> + reg.id = id;
> + reg.addr = (unsigned long)&val;
> + vcpu_set_reg(vm, vcpuid, ®);
> +}
> +
> +/* L3 index Bit[47:39] */
> +#define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL
> +#define PGTBL_L3_INDEX_SHIFT 39
> +#define PGTBL_L3_BLOCK_SHIFT 39
> +#define PGTBL_L3_BLOCK_SIZE 0x0000008000000000ULL
> +#define PGTBL_L3_MAP_MASK (~(PGTBL_L3_BLOCK_SIZE - 1))
> +/* L2 index Bit[38:30] */
> +#define PGTBL_L2_INDEX_MASK 0x0000007FC0000000ULL
> +#define PGTBL_L2_INDEX_SHIFT 30
> +#define PGTBL_L2_BLOCK_SHIFT 30
> +#define PGTBL_L2_BLOCK_SIZE 0x0000000040000000ULL
> +#define PGTBL_L2_MAP_MASK (~(PGTBL_L2_BLOCK_SIZE - 1))
> +/* L1 index Bit[29:21] */
> +#define PGTBL_L1_INDEX_MASK 0x000000003FE00000ULL
> +#define PGTBL_L1_INDEX_SHIFT 21
> +#define PGTBL_L1_BLOCK_SHIFT 21
> +#define PGTBL_L1_BLOCK_SIZE 0x0000000000200000ULL
> +#define PGTBL_L1_MAP_MASK (~(PGTBL_L1_BLOCK_SIZE - 1))
> +/* L0 index Bit[20:12] */
> +#define PGTBL_L0_INDEX_MASK 0x00000000001FF000ULL
> +#define PGTBL_L0_INDEX_SHIFT 12
> +#define PGTBL_L0_BLOCK_SHIFT 12
> +#define PGTBL_L0_BLOCK_SIZE 0x0000000000001000ULL
> +#define PGTBL_L0_MAP_MASK (~(PGTBL_L0_BLOCK_SIZE - 1))
> +
> +#define PGTBL_PTE_ADDR_MASK 0x003FFFFFFFFFFC00ULL
> +#define PGTBL_PTE_ADDR_SHIFT 10
> +#define PGTBL_PTE_RSW_MASK 0x0000000000000300ULL
> +#define PGTBL_PTE_RSW_SHIFT 8
> +#define PGTBL_PTE_DIRTY_MASK 0x0000000000000080ULL
> +#define PGTBL_PTE_DIRTY_SHIFT 7
> +#define PGTBL_PTE_ACCESSED_MASK 0x0000000000000040ULL
> +#define PGTBL_PTE_ACCESSED_SHIFT 6
> +#define PGTBL_PTE_GLOBAL_MASK 0x0000000000000020ULL
> +#define PGTBL_PTE_GLOBAL_SHIFT 5
> +#define PGTBL_PTE_USER_MASK 0x0000000000000010ULL
> +#define PGTBL_PTE_USER_SHIFT 4
> +#define PGTBL_PTE_EXECUTE_MASK 0x0000000000000008ULL
> +#define PGTBL_PTE_EXECUTE_SHIFT 3
> +#define PGTBL_PTE_WRITE_MASK 0x0000000000000004ULL
> +#define PGTBL_PTE_WRITE_SHIFT 2
> +#define PGTBL_PTE_READ_MASK 0x0000000000000002ULL
> +#define PGTBL_PTE_READ_SHIFT 1
> +#define PGTBL_PTE_PERM_MASK (PGTBL_PTE_EXECUTE_MASK | \
> + PGTBL_PTE_WRITE_MASK | \
> + PGTBL_PTE_READ_MASK)
> +#define PGTBL_PTE_VALID_MASK 0x0000000000000001ULL
> +#define PGTBL_PTE_VALID_SHIFT 0
> +
> +#define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE
> +#define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT
> +
> +#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
> +#define SATP_MODE_39 _AC(0x8000000000000000, UL)
> +#define SATP_MODE_48 _AC(0x9000000000000000, UL)
> +#define SATP_ASID_BITS 16
> +#define SATP_ASID_SHIFT 44
> +#define SATP_ASID_MASK _AC(0xFFFF, UL)
> +
> +#define SBI_EXT_EXPERIMENTAL_START 0x08000000
> +#define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF
> +
> +#define KVM_RISCV_SELFTESTS_SBI_EXT SBI_EXT_EXPERIMENTAL_END
> +
> +struct sbiret {
> + long error;
> + long value;
> +};
> +
> +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> + unsigned long arg1, unsigned long arg2,
> + unsigned long arg3, unsigned long arg4,
> + unsigned long arg5);
> +
> +#endif /* SELFTEST_KVM_PROCESSOR_H */
> diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/selftests/kvm/lib/guest_modes.c
> index c330f414ef96..57839a12e472 100644
> --- a/tools/testing/selftests/kvm/lib/guest_modes.c
> +++ b/tools/testing/selftests/kvm/lib/guest_modes.c
> @@ -38,6 +38,16 @@ void guest_modes_append_default(void)
> guest_mode_append(VM_MODE_P47V64_4K, true, true);
> }
> #endif
> +#ifdef __riscv
> + {
> + unsigned int sz = kvm_check_cap(KVM_CAP_VM_GPA_BITS);
> +
> + if (sz >= 52)
> + guest_mode_append(VM_MODE_P52V48_4K, true, true);
> + if (sz >= 48)
> + guest_mode_append(VM_MODE_P48V48_4K, true, true);
> + }
> +#endif
> }
>
> void for_each_guest_mode(void (*func)(enum vm_guest_mode, void *), void *arg)
> diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
> new file mode 100644
> index 000000000000..d377f2603d98
> --- /dev/null
> +++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
> @@ -0,0 +1,362 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * RISC-V code
> + *
> + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> + */
> +
> +#include <linux/compiler.h>
> +#include <assert.h>
> +
> +#include "kvm_util.h"
> +#include "../kvm_util_internal.h"
> +#include "processor.h"
> +
> +#define DEFAULT_RISCV_GUEST_STACK_VADDR_MIN 0xac0000
> +
> +static uint64_t page_align(struct kvm_vm *vm, uint64_t v)
> +{
> + return (v + vm->page_size) & ~(vm->page_size - 1);
> +}
> +
> +static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry)
> +{
> + return ((entry & PGTBL_PTE_ADDR_MASK) >> PGTBL_PTE_ADDR_SHIFT) <<
> + PGTBL_PAGE_SIZE_SHIFT;
> +}
> +
> +static uint64_t ptrs_per_pte(struct kvm_vm *vm)
> +{
> + return PGTBL_PAGE_SIZE / sizeof(uint64_t);
> +}
> +
> +static uint64_t pte_index_mask[] = {
> + PGTBL_L0_INDEX_MASK,
> + PGTBL_L1_INDEX_MASK,
> + PGTBL_L2_INDEX_MASK,
> + PGTBL_L3_INDEX_MASK,
> +};
> +
> +static uint32_t pte_index_shift[] = {
> + PGTBL_L0_INDEX_SHIFT,
> + PGTBL_L1_INDEX_SHIFT,
> + PGTBL_L2_INDEX_SHIFT,
> + PGTBL_L3_INDEX_SHIFT,
> +};
> +
> +static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level)
> +{
> + TEST_ASSERT(level > -1,
> + "Negative page table level (%d) not possible", level);
> + TEST_ASSERT(level < vm->pgtable_levels,
> + "Invalid page table level (%d)", level);
> +
> + return (gva & pte_index_mask[level]) >> pte_index_shift[level];
> +}
> +
> +void virt_pgd_alloc(struct kvm_vm *vm)
> +{
> + if (!vm->pgd_created) {
> + vm_paddr_t paddr = vm_phy_pages_alloc(vm,
> + page_align(vm, ptrs_per_pte(vm) * 8) / vm->page_size,
> + KVM_GUEST_PAGE_TABLE_MIN_PADDR, 0);
> + vm->pgd = paddr;
> + vm->pgd_created = true;
> + }
> +}
> +
> +void virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
> +{
> + uint64_t *ptep, next_ppn;
> + int level = vm->pgtable_levels - 1;
> +
> + TEST_ASSERT((vaddr % vm->page_size) == 0,
> + "Virtual address not on page boundary,\n"
> + " vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size);
> + TEST_ASSERT(sparsebit_is_set(vm->vpages_valid,
> + (vaddr >> vm->page_shift)),
> + "Invalid virtual address, vaddr: 0x%lx", vaddr);
> + TEST_ASSERT((paddr % vm->page_size) == 0,
> + "Physical address not on page boundary,\n"
> + " paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size);
> + TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
> + "Physical address beyond maximum supported,\n"
> + " paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
> + paddr, vm->max_gfn, vm->page_size);
> +
> + ptep = addr_gpa2hva(vm, vm->pgd) + pte_index(vm, vaddr, level) * 8;
> + if (!*ptep) {
> + next_ppn = vm_alloc_page_table(vm) >> PGTBL_PAGE_SIZE_SHIFT;
> + *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) |
> + PGTBL_PTE_VALID_MASK;
> + }
> + level--;
> +
> + while (level > -1) {
> + ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) +
> + pte_index(vm, vaddr, level) * 8;
> + if (!*ptep && level > 0) {
> + next_ppn = vm_alloc_page_table(vm) >>
> + PGTBL_PAGE_SIZE_SHIFT;
> + *ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) |
> + PGTBL_PTE_VALID_MASK;
> + }
> + level--;
> + }
> +
> + paddr = paddr >> PGTBL_PAGE_SIZE_SHIFT;
> + *ptep = (paddr << PGTBL_PTE_ADDR_SHIFT) |
> + PGTBL_PTE_PERM_MASK | PGTBL_PTE_VALID_MASK;
> +}
> +
> +vm_paddr_t addr_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
> +{
> + uint64_t *ptep;
> + int level = vm->pgtable_levels - 1;
> +
> + if (!vm->pgd_created)
> + goto unmapped_gva;
> +
> + ptep = addr_gpa2hva(vm, vm->pgd) + pte_index(vm, gva, level) * 8;
> + if (!ptep)
> + goto unmapped_gva;
> + level--;
> +
> + while (level > -1) {
> + ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) +
> + pte_index(vm, gva, level) * 8;
> + if (!ptep)
> + goto unmapped_gva;
> + level--;
> + }
> +
> + return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1));
> +
> +unmapped_gva:
> + TEST_FAIL("No mapping for vm virtual address gva: 0x%lx level: %d",
> + gva, level);
> + exit(1);
> +}
> +
> +static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent,
> + uint64_t page, int level)
> +{
> +#ifdef DEBUG
> + static const char *const type[] = { "pte", "pmd", "pud", "p4d"};
> + uint64_t pte, *ptep;
> +
> + if (level < 0)
> + return;
> +
> + for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) {
> + ptep = addr_gpa2hva(vm, pte);
> + if (!*ptep)
> + continue;
> + fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "",
> + type[level], pte, *ptep, ptep);
> + pte_dump(stream, vm, indent + 1,
> + pte_addr(vm, *ptep), level - 1);
> + }
> +#endif
> +}
> +
> +void virt_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
> +{
> + int level = vm->pgtable_levels - 1;
> + uint64_t pgd, *ptep;
> +
> + if (!vm->pgd_created)
> + return;
> +
> + for (pgd = vm->pgd; pgd < vm->pgd + ptrs_per_pte(vm) * 8; pgd += 8) {
> + ptep = addr_gpa2hva(vm, pgd);
> + if (!*ptep)
> + continue;
> + fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "",
> + pgd, *ptep, ptep);
> + pte_dump(stream, vm, indent + 1,
> + pte_addr(vm, *ptep), level - 1);
> + }
> +}
> +
> +void riscv_vcpu_mmu_setup(struct kvm_vm *vm, int vcpuid)
> +{
> + unsigned long satp;
> +
> + /*
> + * The RISC-V Sv48 MMU mode supports 56-bit physical address
> + * for 48-bit virtual address with 4KB last level page size.
> + */
> + switch (vm->mode) {
> + case VM_MODE_P52V48_4K:
> + case VM_MODE_P48V48_4K:
> + case VM_MODE_P40V48_4K:
> + break;
> + default:
> + TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode);
> + }
> +
> + satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN;
> + satp |= SATP_MODE_48;
> +
> + set_reg(vm, vcpuid, RISCV_CSR_REG(satp), satp);
> +}
> +
> +void vcpu_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint8_t indent)
> +{
> + struct kvm_riscv_core core;
> +
> + get_reg(vm, vcpuid, RISCV_CORE_REG(mode), &core.mode);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.pc), &core.regs.pc);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.ra), &core.regs.ra);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.sp), &core.regs.sp);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.gp), &core.regs.gp);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.tp), &core.regs.tp);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t0), &core.regs.t0);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t1), &core.regs.t1);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t2), &core.regs.t2);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s0), &core.regs.s0);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s1), &core.regs.s1);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a0), &core.regs.a0);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a1), &core.regs.a1);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a2), &core.regs.a2);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a3), &core.regs.a3);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a4), &core.regs.a4);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a5), &core.regs.a5);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a6), &core.regs.a6);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a7), &core.regs.a7);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s2), &core.regs.s2);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s3), &core.regs.s3);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s4), &core.regs.s4);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s5), &core.regs.s5);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s6), &core.regs.s6);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s7), &core.regs.s7);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s8), &core.regs.s8);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s9), &core.regs.s9);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s10), &core.regs.s10);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s11), &core.regs.s11);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t3), &core.regs.t3);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t4), &core.regs.t4);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t5), &core.regs.t5);
> + get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t6), &core.regs.t6);
> +
> + fprintf(stream,
> + " MODE: 0x%lx\n", core.mode);
> + fprintf(stream,
> + " PC: 0x%016lx RA: 0x%016lx SP: 0x%016lx GP: 0x%016lx\n",
> + core.regs.pc, core.regs.ra, core.regs.sp, core.regs.gp);
> + fprintf(stream,
> + " TP: 0x%016lx T0: 0x%016lx T1: 0x%016lx T2: 0x%016lx\n",
> + core.regs.tp, core.regs.t0, core.regs.t1, core.regs.t2);
> + fprintf(stream,
> + " S0: 0x%016lx S1: 0x%016lx A0: 0x%016lx A1: 0x%016lx\n",
> + core.regs.s0, core.regs.s1, core.regs.a0, core.regs.a1);
> + fprintf(stream,
> + " A2: 0x%016lx A3: 0x%016lx A4: 0x%016lx A5: 0x%016lx\n",
> + core.regs.a2, core.regs.a3, core.regs.a4, core.regs.a5);
> + fprintf(stream,
> + " A6: 0x%016lx A7: 0x%016lx S2: 0x%016lx S3: 0x%016lx\n",
> + core.regs.a6, core.regs.a7, core.regs.s2, core.regs.s3);
> + fprintf(stream,
> + " S4: 0x%016lx S5: 0x%016lx S6: 0x%016lx S7: 0x%016lx\n",
> + core.regs.s4, core.regs.s5, core.regs.s6, core.regs.s7);
> + fprintf(stream,
> + " S8: 0x%016lx S9: 0x%016lx S10: 0x%016lx S11: 0x%016lx\n",
> + core.regs.s8, core.regs.s9, core.regs.s10, core.regs.s11);
> + fprintf(stream,
> + " T3: 0x%016lx T4: 0x%016lx T5: 0x%016lx T6: 0x%016lx\n",
> + core.regs.t3, core.regs.t4, core.regs.t5, core.regs.t6);
> +}
> +
> +static void guest_hang(void)
> +{
> + while (1)
> + ;
> +}
> +
> +void vm_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid, void *guest_code)
> +{
> + int r;
> + size_t stack_size = vm->page_size == 4096 ?
> + DEFAULT_STACK_PGS * vm->page_size :
> + vm->page_size;
> + unsigned long stack_vaddr = vm_vaddr_alloc(vm, stack_size,
> + DEFAULT_RISCV_GUEST_STACK_VADDR_MIN);
> + unsigned long current_gp = 0;
> + struct kvm_mp_state mps;
> +
> + vm_vcpu_add(vm, vcpuid);
> + riscv_vcpu_mmu_setup(vm, vcpuid);
> +
> + /*
> + * With SBI HSM support in KVM RISC-V, all secondary VCPUs are
> + * powered-off by default so we ensure that all secondary VCPUs
> + * are powered-on using KVM_SET_MP_STATE ioctl().
> + */
> + mps.mp_state = KVM_MP_STATE_RUNNABLE;
> + r = _vcpu_ioctl(vm, vcpuid, KVM_SET_MP_STATE, &mps);
> + TEST_ASSERT(!r, "IOCTL KVM_SET_MP_STATE failed (error %d)", r);
> +
> + /* Setup global pointer of guest to be same as the host */
> + asm volatile (
> + "add %0, gp, zero" : "=r" (current_gp) : : "memory");
> + set_reg(vm, vcpuid, RISCV_CORE_REG(regs.gp), current_gp);
> +
> + /* Setup stack pointer and program counter of guest */
> + set_reg(vm, vcpuid, RISCV_CORE_REG(regs.sp),
> + stack_vaddr + stack_size);
> + set_reg(vm, vcpuid, RISCV_CORE_REG(regs.pc),
> + (unsigned long)guest_code);
> +
> + /* Setup default exception vector of guest */
> + set_reg(vm, vcpuid, RISCV_CSR_REG(stvec),
> + (unsigned long)guest_hang);
> +}
> +
> +void vcpu_args_set(struct kvm_vm *vm, uint32_t vcpuid, unsigned int num, ...)
> +{
> + va_list ap;
> + uint64_t id = RISCV_CORE_REG(regs.a0);
> + int i;
> +
> + TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n"
> + " num: %u\n", num);
> +
> + va_start(ap, num);
> +
> + for (i = 0; i < num; i++) {
> + switch (i) {
> + case 0:
> + id = RISCV_CORE_REG(regs.a0);
> + break;
> + case 1:
> + id = RISCV_CORE_REG(regs.a1);
> + break;
> + case 2:
> + id = RISCV_CORE_REG(regs.a2);
> + break;
> + case 3:
> + id = RISCV_CORE_REG(regs.a3);
> + break;
> + case 4:
> + id = RISCV_CORE_REG(regs.a4);
> + break;
> + case 5:
> + id = RISCV_CORE_REG(regs.a5);
> + break;
> + case 6:
> + id = RISCV_CORE_REG(regs.a6);
> + break;
> + case 7:
> + id = RISCV_CORE_REG(regs.a7);
> + break;
> + };
> + set_reg(vm, vcpuid, id, va_arg(ap, uint64_t));
> + }
> +
> + va_end(ap);
> +}
> +
> +void assert_on_unhandled_exception(struct kvm_vm *vm, uint32_t vcpuid)
> +{
> +}
> diff --git a/tools/testing/selftests/kvm/lib/riscv/ucall.c b/tools/testing/selftests/kvm/lib/riscv/ucall.c
> new file mode 100644
> index 000000000000..9e42d8248fa6
> --- /dev/null
> +++ b/tools/testing/selftests/kvm/lib/riscv/ucall.c
> @@ -0,0 +1,87 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * ucall support. A ucall is a "hypercall to userspace".
> + *
> + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> + */
> +
> +#include <linux/kvm.h>
> +
> +#include "kvm_util.h"
> +#include "../kvm_util_internal.h"
> +#include "processor.h"
> +
> +void ucall_init(struct kvm_vm *vm, void *arg)
> +{
> +}
> +
> +void ucall_uninit(struct kvm_vm *vm)
> +{
> +}
> +
> +struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> + unsigned long arg1, unsigned long arg2,
> + unsigned long arg3, unsigned long arg4,
> + unsigned long arg5)
> +{
> + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
> + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
> + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
> + register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
> + register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
> + register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
> + register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
> + register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
> + struct sbiret ret;
> +
> + asm volatile (
> + "ecall"
> + : "+r" (a0), "+r" (a1)
> + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
> + : "memory");
> + ret.error = a0;
> + ret.value = a1;
> +
> + return ret;
> +}
> +
> +void ucall(uint64_t cmd, int nargs, ...)
> +{
> + struct ucall uc = {
> + .cmd = cmd,
> + };
> + va_list va;
> + int i;
> +
> + nargs = nargs <= UCALL_MAX_ARGS ? nargs : UCALL_MAX_ARGS;
> +
> + va_start(va, nargs);
> + for (i = 0; i < nargs; ++i)
> + uc.args[i] = va_arg(va, uint64_t);
> + va_end(va);
> +
> + sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT, 0, (vm_vaddr_t)&uc,
> + 0, 0, 0, 0, 0);
> +}
> +
> +uint64_t get_ucall(struct kvm_vm *vm, uint32_t vcpu_id, struct ucall *uc)
> +{
> + struct kvm_run *run = vcpu_state(vm, vcpu_id);
> + struct ucall ucall = {};
> +
> + if (uc)
> + memset(uc, 0, sizeof(*uc));
> +
> + if (run->exit_reason == KVM_EXIT_RISCV_SBI &&
> + run->riscv_sbi.extension_id == KVM_RISCV_SELFTESTS_SBI_EXT &&
> + run->riscv_sbi.function_id == 0) {
> + memcpy(&ucall, addr_gva2hva(vm, run->riscv_sbi.args[0]),
> + sizeof(ucall));
> +
> + vcpu_run_complete_io(vm, vcpu_id);
> + if (uc)
> + memcpy(uc, &ucall, sizeof(ucall));
> + }
> +
> + return ucall.cmd;
> +}
> --
> 2.25.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 0/4] KVM RISC-V 64-bit selftests support
2021-11-29 7:54 ` Anup Patel
@ 2021-12-22 8:51 ` Atish Patra
-1 siblings, 0 replies; 30+ messages in thread
From: Atish Patra @ 2021-12-22 8:51 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Shuah Khan, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Alistair Francis, Anup Patel, KVM General, kvm-riscv,
linux-riscv, linux-kernel@vger.kernel.org List, linux-kselftest
On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> This series adds initial support for testing KVM RISC-V 64-bit using
> kernel selftests framework. The PATCH1 & PATCH2 of this series does
> some ground work in KVM RISC-V to implement RISC-V support in the KVM
> selftests whereas remaining patches does required changes in the KVM
> selftests.
>
> These patches can be found in riscv_kvm_selftests_v2 branch at:
> https://github.com/avpatel/linux.git
>
> Changes since v1:
> - Renamed kvm_sbi_ext_expevend_handler() to kvm_sbi_ext_forward_handler()
> in PATCH1
> - Renamed KVM_CAP_RISCV_VM_GPA_SIZE to KVM_CAP_VM_GPA_BITS in PATCH2
> and PATCH4
>
> Anup Patel (4):
> RISC-V: KVM: Forward SBI experimental and vendor extensions
> RISC-V: KVM: Add VM capability to allow userspace get GPA bits
> KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
> KVM: selftests: Add initial support for RISC-V 64-bit
>
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/kvm/mmu.c | 5 +
> arch/riscv/kvm/vcpu_sbi.c | 4 +
> arch/riscv/kvm/vcpu_sbi_base.c | 27 ++
> arch/riscv/kvm/vm.c | 3 +
> include/uapi/linux/kvm.h | 1 +
> tools/testing/selftests/kvm/Makefile | 14 +-
> .../testing/selftests/kvm/include/kvm_util.h | 10 +
> .../selftests/kvm/include/riscv/processor.h | 135 +++++++
> tools/testing/selftests/kvm/lib/guest_modes.c | 10 +
> .../selftests/kvm/lib/riscv/processor.c | 362 ++++++++++++++++++
> tools/testing/selftests/kvm/lib/riscv/ucall.c | 87 +++++
> 12 files changed, 658 insertions(+), 1 deletion(-)
> create mode 100644 tools/testing/selftests/kvm/include/riscv/processor.h
> create mode 100644 tools/testing/selftests/kvm/lib/riscv/processor.c
> create mode 100644 tools/testing/selftests/kvm/lib/riscv/ucall.c
>
> --
> 2.25.1
>
For the entire series,
Tested-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v2 0/4] KVM RISC-V 64-bit selftests support
@ 2021-12-22 8:51 ` Atish Patra
0 siblings, 0 replies; 30+ messages in thread
From: Atish Patra @ 2021-12-22 8:51 UTC (permalink / raw)
To: Anup Patel
Cc: Paolo Bonzini, Shuah Khan, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Alistair Francis, Anup Patel, KVM General, kvm-riscv,
linux-riscv, linux-kernel@vger.kernel.org List, linux-kselftest
On Mon, Nov 29, 2021 at 12:10 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> This series adds initial support for testing KVM RISC-V 64-bit using
> kernel selftests framework. The PATCH1 & PATCH2 of this series does
> some ground work in KVM RISC-V to implement RISC-V support in the KVM
> selftests whereas remaining patches does required changes in the KVM
> selftests.
>
> These patches can be found in riscv_kvm_selftests_v2 branch at:
> https://github.com/avpatel/linux.git
>
> Changes since v1:
> - Renamed kvm_sbi_ext_expevend_handler() to kvm_sbi_ext_forward_handler()
> in PATCH1
> - Renamed KVM_CAP_RISCV_VM_GPA_SIZE to KVM_CAP_VM_GPA_BITS in PATCH2
> and PATCH4
>
> Anup Patel (4):
> RISC-V: KVM: Forward SBI experimental and vendor extensions
> RISC-V: KVM: Add VM capability to allow userspace get GPA bits
> KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile
> KVM: selftests: Add initial support for RISC-V 64-bit
>
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/kvm/mmu.c | 5 +
> arch/riscv/kvm/vcpu_sbi.c | 4 +
> arch/riscv/kvm/vcpu_sbi_base.c | 27 ++
> arch/riscv/kvm/vm.c | 3 +
> include/uapi/linux/kvm.h | 1 +
> tools/testing/selftests/kvm/Makefile | 14 +-
> .../testing/selftests/kvm/include/kvm_util.h | 10 +
> .../selftests/kvm/include/riscv/processor.h | 135 +++++++
> tools/testing/selftests/kvm/lib/guest_modes.c | 10 +
> .../selftests/kvm/lib/riscv/processor.c | 362 ++++++++++++++++++
> tools/testing/selftests/kvm/lib/riscv/ucall.c | 87 +++++
> 12 files changed, 658 insertions(+), 1 deletion(-)
> create mode 100644 tools/testing/selftests/kvm/include/riscv/processor.h
> create mode 100644 tools/testing/selftests/kvm/lib/riscv/processor.c
> create mode 100644 tools/testing/selftests/kvm/lib/riscv/ucall.c
>
> --
> 2.25.1
>
For the entire series,
Tested-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2021-12-22 8:51 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-11-29 7:54 [PATCH v2 0/4] KVM RISC-V 64-bit selftests support Anup Patel
2021-11-29 7:54 ` Anup Patel
2021-11-29 7:54 ` [PATCH v2 1/4] RISC-V: KVM: Forward SBI experimental and vendor extensions Anup Patel
2021-11-29 7:54 ` Anup Patel
2021-12-17 5:42 ` Atish Patra
2021-12-17 5:42 ` Atish Patra
2021-11-29 7:54 ` [PATCH v2 2/4] RISC-V: KVM: Add VM capability to allow userspace get GPA bits Anup Patel
2021-11-29 7:54 ` Anup Patel
2021-12-17 5:47 ` Atish Patra
2021-12-17 5:47 ` Atish Patra
2021-12-17 6:08 ` Anup Patel
2021-12-17 6:08 ` Anup Patel
2021-12-17 8:28 ` Paolo Bonzini
2021-12-17 8:28 ` Paolo Bonzini
2021-11-29 7:54 ` [PATCH v2 3/4] KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile Anup Patel
2021-11-29 7:54 ` Anup Patel
2021-12-17 5:50 ` Atish Patra
2021-12-17 5:50 ` Atish Patra
2021-12-20 19:45 ` Sean Christopherson
2021-12-20 19:45 ` Sean Christopherson
2021-12-21 9:18 ` Anup Patel
2021-12-21 9:18 ` Anup Patel
2021-11-29 7:54 ` [PATCH v2 4/4] KVM: selftests: Add initial support for RISC-V 64-bit Anup Patel
2021-11-29 7:54 ` Anup Patel
2021-12-22 8:48 ` Atish Patra
2021-12-22 8:48 ` Atish Patra
2021-12-11 3:41 ` [PATCH v2 0/4] KVM RISC-V 64-bit selftests support Anup Patel
2021-12-11 3:41 ` Anup Patel
2021-12-22 8:51 ` Atish Patra
2021-12-22 8:51 ` Atish Patra
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