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Sat, 17 Apr 2021 23:37:39 -0400 Received: from mail-io1-xd2e.google.com (mail-io1-xd2e.google.com [IPv6:2607:f8b0:4864:20::d2e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 010DDC06174A for ; Sat, 17 Apr 2021 20:37:11 -0700 (PDT) Received: by mail-io1-xd2e.google.com with SMTP id p8so10187089iol.11 for ; Sat, 17 Apr 2021 20:37:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atishpatra.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=UmV0DZTEAz6CSbuv2cgSZLxj29FZdNHrKuNFU6SEkpk=; b=ReOA1xmcTGTlYDe2rWwZGwuO4KmkS8yPypxDhxZuMihDdj4a3FqTz8FIgoFnYyVpjz tS/xOu1yKE81LPO2DlfT9DOgVCv0TXkE9o4GzJ8qOAFAJgQLojol3BrWYp1DMhW0CSBX 5teNQbC3ertAueFcYsLoR+X6CSYkrqPIwIpos= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=UmV0DZTEAz6CSbuv2cgSZLxj29FZdNHrKuNFU6SEkpk=; b=YZoyxeYVJF3bguefrh8aJe8upiGSXQ8qPI80OnMz/DpR8wE8MF029Y02CR6tNNNPFE rkLewoNtxGvADma1R6x+USp+jtrPj4arpx7nM9gtipLV6oe0z/yNfJXcvBVhKXlcQGLU q3q+m8BmsGZD4BziU2IAqJno4G0b2MSJiheBRYRmPZgAUZvkS6a5DdNxXP/nroqXMJoQ oy5wOm/7Ldw7625CLp3OJ6fJIZiJEIkx1RUs5vYXsa00l/ajz8ldjuIxL3jD3mB22AFr F3JDxwz9q0eOSmPd8KPkZzhEZSyLcX/f06k2WXCir4EaFRHnwcoROdMJRvo4MGW2F4ji 0y+A== X-Gm-Message-State: AOAM5332fQT+1laIFEYts04gK6pZi+D6kKYOpgyOapq03H3EgGd2h69a Sb6W08B2p+uWmwJM20t/U1UEjffzy9rwh5JuhYZm X-Google-Smtp-Source: ABdhPJxWRoO2O8Rk4+agTiYNECrlV7E3MqTTFhteAO/qtJbYbiTws+kqeJQmA5hyNyDjqbk1wfWu6TQCUdkpxddPMVs= X-Received: by 2002:a5e:8304:: with SMTP id x4mr9372252iom.53.1618717031181; Sat, 17 Apr 2021 20:37:11 -0700 (PDT) MIME-Version: 1.0 References: <20210303200253.1827553-1-atish.patra@wdc.com> <20210303200253.1827553-4-atish.patra@wdc.com> <7eb2b954-6b0a-b143-9107-57f4dd90d0cf@ghiti.fr> In-Reply-To: From: Atish Patra Date: Sat, 17 Apr 2021 20:36:59 -0700 Message-ID: Subject: Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board To: Vitaly Wool Cc: Alex Ghiti , Atish Patra , LKML , Albert Ou , Alistair Francis , Anup Patel , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , devicetree , linux-riscv , Palmer Dabbelt , Paul Walmsley , Rob Herring , Conor.Dooley@microchip.com, Daire McNamara , Ivan.Griffin@microchip.com, Lewis.Hanly@microchip.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 29, 2021 at 10:04 AM Vitaly Wool wro= te: > > On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti wrote: > > > > Hi Atish, > > > > Le 3/3/21 =C3=A0 3:02 PM, Atish Patra a =C3=A9crit : > > > Add initial DTS for Microchip ICICLE board having only > > > essential devices (clocks, sdhci, ethernet, serial, etc). > > > The device tree is based on the U-Boot patch. > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142= -6-padmarao.begari@microchip.com/ > > > > > > Signed-off-by: Atish Patra > > > --- > > > arch/riscv/boot/dts/Makefile | 1 + > > > arch/riscv/boot/dts/microchip/Makefile | 2 + > > > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > > > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 +++++++++++++++= +++ > > > 4 files changed, 404 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-ici= cle-kit.dts > > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dts= i > > > > > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makef= ile > > > index 7ffd502e3e7b..fe996b88319e 100644 > > > --- a/arch/riscv/boot/dts/Makefile > > > +++ b/arch/riscv/boot/dts/Makefile > > > @@ -1,5 +1,6 @@ > > > # SPDX-License-Identifier: GPL-2.0 > > > subdir-y +=3D sifive > > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) +=3D canaan > > > +subdir-y +=3D microchip > > > > > > obj-$(CONFIG_BUILTIN_DTB) :=3D $(addsuffix /, $(subdir-y)) > > > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot= /dts/microchip/Makefile > > > new file mode 100644 > > > index 000000000000..622b12771fd3 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/microchip/Makefile > > > @@ -0,0 +1,2 @@ > > > +# SPDX-License-Identifier: GPL-2.0 > > > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D microchip-mpfs-icicle-kit= .dtb > > > > I'm playing (or trying to...) with XIP_KERNEL and I had to add the > > following to have the device tree actually builtin the kernel: > > > > diff --git a/arch/riscv/boot/dts/microchip/Makefile > > b/arch/riscv/boot/dts/microchip/Makefile > > index 622b12771fd3..855c1502d912 100644 > > --- a/arch/riscv/boot/dts/microchip/Makefile > > +++ b/arch/riscv/boot/dts/microchip/Makefile > > @@ -1,2 +1,3 @@ > > # SPDX-License-Identifier: GPL-2.0 > > dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D microchip-mpfs-icicle-kit.= dtb > > +obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) > > > > Alex > > Yes, I believe this is necessary for BUILTIN_DTB to work on Polarfire, > regardless of whether the kernel is XIP or not. > But there is no usecase for BUILTIN_DTB for polarfire except XIP kernel. The bootloaders for polarfire is capable of providing a DTB to kernel. If XIP kernel is enabled, the following line in arch/riscv/boot/dts/Makefile should take care of things > Best regards, > Vitaly > > > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.= dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > > new file mode 100644 > > > index 000000000000..ec79944065c9 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > > @@ -0,0 +1,72 @@ > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > > + > > > +/dts-v1/; > > > + > > > +#include "microchip-mpfs.dtsi" > > > + > > > +/* Clock frequency (in Hz) of the rtcclk */ > > > +#define RTCCLK_FREQ 1000000 > > > + > > > +/ { > > > + #address-cells =3D <2>; > > > + #size-cells =3D <2>; > > > + model =3D "Microchip PolarFire-SoC Icicle Kit"; > > > + compatible =3D "microchip,mpfs-icicle-kit"; > > > + > > > + chosen { > > > + stdout-path =3D &serial0; > > > + }; > > > + > > > + cpus { > > > + timebase-frequency =3D ; > > > + }; > > > + > > > + memory@80000000 { > > > + device_type =3D "memory"; > > > + reg =3D <0x0 0x80000000 0x0 0x40000000>; > > > + clocks =3D <&clkcfg 26>; > > > + }; > > > + > > > + soc { > > > + }; > > > +}; > > > + > > > +&serial0 { > > > + status =3D "okay"; > > > +}; > > > + > > > +&serial1 { > > > + status =3D "okay"; > > > +}; > > > + > > > +&serial2 { > > > + status =3D "okay"; > > > +}; > > > + > > > +&serial3 { > > > + status =3D "okay"; > > > +}; > > > + > > > +&sdcard { > > > + status =3D "okay"; > > > +}; > > > + > > > +&emac0 { > > > + phy-mode =3D "sgmii"; > > > + phy-handle =3D <&phy0>; > > > + phy0: ethernet-phy@8 { > > > + reg =3D <8>; > > > + ti,fifo-depth =3D <0x01>; > > > + }; > > > +}; > > > + > > > +&emac1 { > > > + status =3D "okay"; > > > + phy-mode =3D "sgmii"; > > > + phy-handle =3D <&phy1>; > > > + phy1: ethernet-phy@9 { > > > + reg =3D <9>; > > > + ti,fifo-depth =3D <0x01>; > > > + }; > > > +}; > > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch= /riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > new file mode 100644 > > > index 000000000000..b9819570a7d1 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > @@ -0,0 +1,329 @@ > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > > + > > > +/dts-v1/; > > > + > > > +/ { > > > + #address-cells =3D <2>; > > > + #size-cells =3D <2>; > > > + model =3D "Microchip MPFS Icicle Kit"; > > > + compatible =3D "microchip,mpfs-icicle-kit"; > > > + > > > + chosen { > > > + }; > > > + > > > + cpus { > > > + #address-cells =3D <1>; > > > + #size-cells =3D <0>; > > > + > > > + cpu@0 { > > > + clock-frequency =3D <0>; > > > + compatible =3D "sifive,e51", "sifive,rocket0", = "riscv"; > > > + device_type =3D "cpu"; > > > + i-cache-block-size =3D <64>; > > > + i-cache-sets =3D <128>; > > > + i-cache-size =3D <16384>; > > > + reg =3D <0>; > > > + riscv,isa =3D "rv64imac"; > > > + status =3D "disabled"; > > > + > > > + cpu0_intc: interrupt-controller { > > > + #interrupt-cells =3D <1>; > > > + compatible =3D "riscv,cpu-intc"; > > > + interrupt-controller; > > > + }; > > > + }; > > > + > > > + cpu@1 { > > > + clock-frequency =3D <0>; > > > + compatible =3D "sifive,u54-mc", "sifive,rocket0= ", "riscv"; > > > + d-cache-block-size =3D <64>; > > > + d-cache-sets =3D <64>; > > > + d-cache-size =3D <32768>; > > > + d-tlb-sets =3D <1>; > > > + d-tlb-size =3D <32>; > > > + device_type =3D "cpu"; > > > + i-cache-block-size =3D <64>; > > > + i-cache-sets =3D <64>; > > > + i-cache-size =3D <32768>; > > > + i-tlb-sets =3D <1>; > > > + i-tlb-size =3D <32>; > > > + mmu-type =3D "riscv,sv39"; > > > + reg =3D <1>; > > > + riscv,isa =3D "rv64imafdc"; > > > + tlb-split; > > > + status =3D "okay"; > > > + > > > + cpu1_intc: interrupt-controller { > > > + #interrupt-cells =3D <1>; > > > + compatible =3D "riscv,cpu-intc"; > > > + interrupt-controller; > > > + }; > > > + }; > > > + > > > + cpu@2 { > > > + clock-frequency =3D <0>; > > > + compatible =3D "sifive,u54-mc", "sifive,rocket0= ", "riscv"; > > > + d-cache-block-size =3D <64>; > > > + d-cache-sets =3D <64>; > > > + d-cache-size =3D <32768>; > > > + d-tlb-sets =3D <1>; > > > + d-tlb-size =3D <32>; > > > + device_type =3D "cpu"; > > > + i-cache-block-size =3D <64>; > > > + i-cache-sets =3D <64>; > > > + i-cache-size =3D <32768>; > > > + i-tlb-sets =3D <1>; > > > + i-tlb-size =3D <32>; > > > + mmu-type =3D "riscv,sv39"; > > > + reg =3D <2>; > > > + riscv,isa =3D "rv64imafdc"; > > > + tlb-split; > > > + status =3D "okay"; > > > + > > > + cpu2_intc: interrupt-controller { > > > + #interrupt-cells =3D <1>; > > > + compatible =3D "riscv,cpu-intc"; > > > + interrupt-controller; > > > + }; > > > + }; > > > + > > > + cpu@3 { > > > + clock-frequency =3D <0>; > > > + compatible =3D "sifive,u54-mc", "sifive,rocket0= ", "riscv"; > > > + d-cache-block-size =3D <64>; > > > + d-cache-sets =3D <64>; > > > + d-cache-size =3D <32768>; > > > + d-tlb-sets =3D <1>; > > > + d-tlb-size =3D <32>; > > > + device_type =3D "cpu"; > > > + i-cache-block-size =3D <64>; > > > + i-cache-sets =3D <64>; > > > + i-cache-size =3D <32768>; > > > + i-tlb-sets =3D <1>; > > > + i-tlb-size =3D <32>; > > > + mmu-type =3D "riscv,sv39"; > > > + reg =3D <3>; > > > + riscv,isa =3D "rv64imafdc"; > > > + tlb-split; > > > + status =3D "okay"; > > > + > > > + cpu3_intc: interrupt-controller { > > > + #interrupt-cells =3D <1>; > > > + compatible =3D "riscv,cpu-intc"; > > > + interrupt-controller; > > > + }; > > > + }; > > > + > > > + cpu@4 { > > > + clock-frequency =3D <0>; > > > + compatible =3D "sifive,u54-mc", "sifive,rocket0= ", "riscv"; > > > + d-cache-block-size =3D <64>; > > > + d-cache-sets =3D <64>; > > > + d-cache-size =3D <32768>; > > > + d-tlb-sets =3D <1>; > > > + d-tlb-size =3D <32>; > > > + device_type =3D "cpu"; > > > + i-cache-block-size =3D <64>; > > > + i-cache-sets =3D <64>; > > > + i-cache-size =3D <32768>; > > > + i-tlb-sets =3D <1>; > > > + i-tlb-size =3D <32>; > > > + mmu-type =3D "riscv,sv39"; > > > + reg =3D <4>; > > > + riscv,isa =3D "rv64imafdc"; > > > + tlb-split; > > > + status =3D "okay"; > > > + cpu4_intc: interrupt-controller { > > > + #interrupt-cells =3D <1>; > > > + compatible =3D "riscv,cpu-intc"; > > > + interrupt-controller; > > > + }; > > > + }; > > > + }; > > > + > > > + soc { > > > + #address-cells =3D <2>; > > > + #size-cells =3D <2>; > > > + compatible =3D "simple-bus"; > > > + ranges; > > > + > > > + cache-controller@2010000 { > > > + compatible =3D "sifive,fu540-c000-ccache", "cac= he"; > > > + cache-block-size =3D <64>; > > > + cache-level =3D <2>; > > > + cache-sets =3D <1024>; > > > + cache-size =3D <2097152>; > > > + cache-unified; > > > + interrupt-parent =3D <&plic>; > > > + interrupts =3D <1 2 3>; > > > + reg =3D <0x0 0x2010000 0x0 0x1000>; > > > + }; > > > + > > > + clint@2000000 { > > > + compatible =3D "sifive,clint0"; > > > + reg =3D <0x0 0x2000000 0x0 0xC000>; > > > + interrupts-extended =3D <&cpu0_intc 3 &cpu0_int= c 7 > > > + &cpu1_intc 3 &cpu1_intc= 7 > > > + &cpu2_intc 3 &cpu2_intc= 7 > > > + &cpu3_intc 3 &cpu3_intc= 7 > > > + &cpu4_intc 3 &cpu4_intc= 7>; > > > + }; > > > + > > > + plic: interrupt-controller@c000000 { > > > + #interrupt-cells =3D <1>; > > > + compatible =3D "sifive,plic-1.0.0"; > > > + reg =3D <0x0 0xc000000 0x0 0x4000000>; > > > + riscv,ndev =3D <186>; > > > + interrupt-controller; > > > + interrupts-extended =3D <&cpu0_intc 11 > > > + &cpu1_intc 11 &cpu1_intc 9 > > > + &cpu2_intc 11 &cpu2_intc 9 > > > + &cpu3_intc 11 &cpu3_intc 9 > > > + &cpu4_intc 11 &cpu4_intc 9>; > > > + }; > > > + > > > + dma@3000000 { > > > + compatible =3D "sifive,fu540-c000-pdma"; > > > + reg =3D <0x0 0x3000000 0x0 0x8000>; > > > + interrupt-parent =3D <&plic>; > > > + interrupts =3D <23 24 25 26 27 28 29 30>; > > > + #dma-cells =3D <1>; > > > + }; > > > + > > > + refclk: refclk { > > > + compatible =3D "fixed-clock"; > > > + #clock-cells =3D <0>; > > > + clock-frequency =3D <600000000>; > > > + clock-output-names =3D "msspllclk"; > > > + }; > > > + > > > + clkcfg: clkcfg@20002000 { > > > + compatible =3D "microchip,mpfs-clkcfg"; > > > + reg =3D <0x0 0x20002000 0x0 0x1000>; > > > + reg-names =3D "mss_sysreg"; > > > + clocks =3D <&refclk>; > > > + #clock-cells =3D <1>; > > > + clock-output-names =3D "cpu", "axi", "ahb", "en= vm", /* 0-3 */ > > > + "mac0", "mac1", "mmc", "timer", = /* 4-7 */ > > > + "mmuart0", "mmuart1", "mmuart2", "mmuar= t3", /* 8-11 */ > > > + "mmuart4", "spi0", "spi1", "i2c0", = /* 12-15 */ > > > + "i2c1", "can0", "can1", "usb", = /* 16-19 */ > > > + "rsvd", "rtc", "qspi", "gpio0", = /* 20-23 */ > > > + "gpio1", "gpio2", "ddrc", "fic0", = /* 24-27 */ > > > + "fic1", "fic2", "fic3", "athena", "cfm"= ; /* 28-32 */ > > > + }; > > > + > > > + serial0: serial@20000000 { > > > + compatible =3D "ns16550a"; > > > + reg =3D <0x0 0x20000000 0x0 0x400>; > > > + reg-io-width =3D <4>; > > > + reg-shift =3D <2>; > > > + interrupt-parent =3D <&plic>; > > > + interrupts =3D <90>; > > > + current-speed =3D <115200>; > > > + clocks =3D <&clkcfg 8>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + serial1: serial@20100000 { > > > + compatible =3D "ns16550a"; > > > + reg =3D <0x0 0x20100000 0x0 0x400>; > > > + reg-io-width =3D <4>; > > > + reg-shift =3D <2>; > > > + interrupt-parent =3D <&plic>; > > > + interrupts =3D <91>; > > > + current-speed =3D <115200>; > > > + clocks =3D <&clkcfg 9>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + serial2: serial@20102000 { > > > + compatible =3D "ns16550a"; > > > + reg =3D <0x0 0x20102000 0x0 0x400>; > > > + reg-io-width =3D <4>; > > > + reg-shift =3D <2>; > > > + interrupt-parent =3D <&plic>; > > > + interrupts =3D <92>; > > > + current-speed =3D <115200>; > > > + clocks =3D <&clkcfg 10>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + serial3: serial@20104000 { > > > + compatible =3D "ns16550a"; > > > + reg =3D <0x0 0x20104000 0x0 0x400>; > > > + reg-io-width =3D <4>; > > > + reg-shift =3D <2>; > > > + interrupt-parent =3D <&plic>; > > > + interrupts =3D <93>; > > > + current-speed =3D <115200>; > > > + clocks =3D <&clkcfg 11>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + emmc: mmc@20008000 { > > > + compatible =3D "cdns,sd4hc"; > > > + reg =3D <0x0 0x20008000 0x0 0x1000>; > > > + interrupt-parent =3D <&plic>; > > > + interrupts =3D <88 89>; > > > + pinctrl-names =3D "default"; > > > + clocks =3D <&clkcfg 6>; > > > + bus-width =3D <4>; > > > + cap-mmc-highspeed; > > > + mmc-ddr-3_3v; > > > + max-frequency =3D <200000000>; > > > + non-removable; > > > + no-sd; > > > + no-sdio; > > > + voltage-ranges =3D <3300 3300>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + sdcard: sdhc@20008000 { > > > + compatible =3D "cdns,sd4hc"; > > > + reg =3D <0x0 0x20008000 0x0 0x1000>; > > > + interrupt-parent =3D <&plic>; > > > + interrupts =3D <88>; > > > + pinctrl-names =3D "default"; > > > + clocks =3D <&clkcfg 6>; > > > + bus-width =3D <4>; > > > + disable-wp; > > > + cap-sd-highspeed; > > > + card-detect-delay =3D <200>; > > > + sd-uhs-sdr12; > > > + sd-uhs-sdr25; > > > + sd-uhs-sdr50; > > > + sd-uhs-sdr104; > > > + max-frequency =3D <200000000>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + emac0: ethernet@20110000 { > > > + compatible =3D "cdns,macb"; > > > + reg =3D <0x0 0x20110000 0x0 0x2000>; > > > + interrupt-parent =3D <&plic>; > > > + interrupts =3D <64 65 66 67>; > > > + local-mac-address =3D [00 00 00 00 00 00]; > > > + clocks =3D <&clkcfg 4>, <&clkcfg 2>; > > > + clock-names =3D "pclk", "hclk"; > > > + status =3D "disabled"; > > > + #address-cells =3D <1>; > > > + #size-cells =3D <0>; > > > + }; > > > + > > > + emac1: ethernet@20112000 { > > > + compatible =3D "cdns,macb"; > > > + reg =3D <0x0 0x20112000 0x0 0x2000>; > > > + interrupt-parent =3D <&plic>; > > > + interrupts =3D <70 71 72 73>; > > > + mac-address =3D [00 00 00 00 00 00]; > > > + clocks =3D <&clkcfg 5>, <&clkcfg 2>; > > > + status =3D "disabled"; > > > + clock-names =3D "pclk", "hclk"; > > > + #address-cells =3D <1>; > > > + #size-cells =3D <0>; > > > + }; > > > + > > > + }; > > > +}; > > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv --=20 Regards, Atish From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, 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mail-io1-xd2e.google.com with SMTP id g125so2895266iof.3 for ; Sat, 17 Apr 2021 20:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atishpatra.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=UmV0DZTEAz6CSbuv2cgSZLxj29FZdNHrKuNFU6SEkpk=; b=ReOA1xmcTGTlYDe2rWwZGwuO4KmkS8yPypxDhxZuMihDdj4a3FqTz8FIgoFnYyVpjz tS/xOu1yKE81LPO2DlfT9DOgVCv0TXkE9o4GzJ8qOAFAJgQLojol3BrWYp1DMhW0CSBX 5teNQbC3ertAueFcYsLoR+X6CSYkrqPIwIpos= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=UmV0DZTEAz6CSbuv2cgSZLxj29FZdNHrKuNFU6SEkpk=; b=Vka64GZFq4rh8vZujhsEMza3/emzpz1K/+znqmILms/D1XmAKVyN+/vv1vDwn1nv+a yL7tLEUnnoh6ox2e1Y00rISCBHMmGUS1W3rM4qDSt0b5kwGtb489BYTAdNvM7pFCLvfi W9PXVisnQ7kop7FiCf/X02cL4xQ6JCUh3BWeqnmt7sv6wT9xAxNs+S2C6hea2ow5xwco 0XV3P2+3jVwYPp8ksZIXgxKb76QYReVQwZPCicFnHaC8Ys3Qa9/d8W6Z8h559KPl8/JN d3jyG41eRllwm1WgiOl7AfltWQJhoNCmTORExijbN/3V4cYHLFc/pS9XUvjbScN7Rkj6 euOA== X-Gm-Message-State: AOAM5337kbrMdpSHmfj0o5X+G5WAjltfHC4ryAtingBd/VVJ7tOEKCnf b+Wl+Og/V4JkLTDx6SRLc1hbWeehEt3OH1u5bHZe X-Google-Smtp-Source: ABdhPJxWRoO2O8Rk4+agTiYNECrlV7E3MqTTFhteAO/qtJbYbiTws+kqeJQmA5hyNyDjqbk1wfWu6TQCUdkpxddPMVs= X-Received: by 2002:a5e:8304:: with SMTP id x4mr9372252iom.53.1618717031181; Sat, 17 Apr 2021 20:37:11 -0700 (PDT) MIME-Version: 1.0 References: <20210303200253.1827553-1-atish.patra@wdc.com> <20210303200253.1827553-4-atish.patra@wdc.com> <7eb2b954-6b0a-b143-9107-57f4dd90d0cf@ghiti.fr> In-Reply-To: From: Atish Patra Date: Sat, 17 Apr 2021 20:36:59 -0700 Message-ID: Subject: Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board To: Vitaly Wool Cc: Alex Ghiti , Atish Patra , LKML , Albert Ou , Alistair Francis , Anup Patel , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , devicetree , linux-riscv , Palmer Dabbelt , Paul Walmsley , Rob Herring , Conor.Dooley@microchip.com, Daire McNamara , Ivan.Griffin@microchip.com, Lewis.Hanly@microchip.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210417_203715_380668_E842EB7E X-CRM114-Status: GOOD ( 24.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gTW9uLCBNYXIgMjksIDIwMjEgYXQgMTA6MDQgQU0gVml0YWx5IFdvb2wgPHZpdGFseS53b29s QGtvbnN1bGtvLmNvbT4gd3JvdGU6Cj4KPiBPbiBTYXQsIE1hciAyNywgMjAyMSBhdCA2OjI0IFBN IEFsZXggR2hpdGkgPGFsZXhAZ2hpdGkuZnI+IHdyb3RlOgo+ID4KPiA+IEhpIEF0aXNoLAo+ID4K PiA+IExlIDMvMy8yMSDDoCAzOjAyIFBNLCBBdGlzaCBQYXRyYSBhIMOpY3JpdCA6Cj4gPiA+IEFk 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