From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EDACC433EF for ; Thu, 26 May 2022 22:55:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348957AbiEZWyy (ORCPT ); Thu, 26 May 2022 18:54:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349300AbiEZWyf (ORCPT ); Thu, 26 May 2022 18:54:35 -0400 Received: from mail-yw1-x112a.google.com (mail-yw1-x112a.google.com [IPv6:2607:f8b0:4864:20::112a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7ADB8EABAF for ; Thu, 26 May 2022 15:54:34 -0700 (PDT) Received: by mail-yw1-x112a.google.com with SMTP id 00721157ae682-2f83983782fso30669667b3.6 for ; Thu, 26 May 2022 15:54:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atishpatra.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=w9bg+crCjcsCCT/8h3P6Is3peQSYKpx7Yjut2+MuLpo=; b=J9BFbfwXM92YHYo1pMX9ukbHtBF65rYzCKp1SEODqtfOWVCqvC1kpJ6Gx+6e25KsXx 7dXCLexRSucYejUcHQzOHbDQkvIK0DDJ1C4R9pGPO9oJyX8xhIz0VeZLSF84V61l4zzO gI/sGQb0hwqh6SzlSHeraOUVufItGmBY08l/A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=w9bg+crCjcsCCT/8h3P6Is3peQSYKpx7Yjut2+MuLpo=; b=UFELhZxmwtyPG08YQ8s9sscRw9KXbbaxO3sMXiz+7wSocUS3NB8OgAHOCbi/6N+tZX 6tZ3FIPedsil+jUji54S1SvHdVhpWi11aTzxmJMOHSX4T8lsSRHqIGO6ceszAsEaUhH8 qc9pQA3lGy89GIeIuQDk3lB1XAzMrPU46qJKRS2Ez28uUPkpjyH6Qm5+oORFGTTps4B7 Iea5hzQUfWlOf8AEpLTiGn7TmV1os2Cm+3kLphietV3unV0KMZT3WbQAZN4ciUgs19EO KTO3rTgeHiU+aQlUhmLmnIJbz24vx+B9wOQC57KofG821LIlPbp9VVjIHCoOPS+7ql2k dJOg== X-Gm-Message-State: AOAM531/wKQSAK0K1a0jWfUARZs2EKETC5MLul6wv4taYGb+Va/SeyIg wFAGDvKRI6E0xQStiyzuUij3FRph0bdlzgIlAW98 X-Google-Smtp-Source: ABdhPJzygxe4mJbRicGsvX2RuWGHFEoIpEz1ZlS3KbXSJc+1j/7lums2g1CvEJbfk0hVJxaHTik5jNooh1w7+04S4Jg= X-Received: by 2002:a81:238e:0:b0:300:642f:fdb2 with SMTP id j136-20020a81238e000000b00300642ffdb2mr8594216ywj.373.1653605673706; Thu, 26 May 2022 15:54:33 -0700 (PDT) MIME-Version: 1.0 References: <20220526101131.2340729-1-sunilvl@ventanamicro.com> <20220526101131.2340729-2-sunilvl@ventanamicro.com> In-Reply-To: <20220526101131.2340729-2-sunilvl@ventanamicro.com> From: Atish Patra Date: Thu, 26 May 2022 15:54:22 -0700 Message-ID: Subject: Re: [PATCH V2 1/5] riscv: cpu_ops_sbi: Support for 64bit hartid To: Sunil V L Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel , linux-riscv , "linux-kernel@vger.kernel.org List" , linux-efi , Sunil V L Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 26, 2022 at 3:11 AM Sunil V L wrote: > > The hartid can be a 64bit value on RV64 platforms. This patch modifies > the hartid variable type to unsigned long so that it can hold 64bit > value on RV64 platforms. > > Signed-off-by: Sunil V L > Reviewed-by: Heinrich Schuchardt > --- > arch/riscv/kernel/cpu_ops_sbi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sbi.c > index 4f5a6f84e2a4..efa0f0816634 100644 > --- a/arch/riscv/kernel/cpu_ops_sbi.c > +++ b/arch/riscv/kernel/cpu_ops_sbi.c > @@ -65,7 +65,7 @@ static int sbi_hsm_hart_get_status(unsigned long hartid) > static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle) > { > unsigned long boot_addr = __pa_symbol(secondary_start_sbi); > - int hartid = cpuid_to_hartid_map(cpuid); > + unsigned long hartid = cpuid_to_hartid_map(cpuid); > unsigned long hsm_data; > struct sbi_hart_boot_data *bdata = &per_cpu(boot_data, cpuid); > > @@ -107,7 +107,7 @@ static void sbi_cpu_stop(void) > static int sbi_cpu_is_stopped(unsigned int cpuid) > { > int rc; > - int hartid = cpuid_to_hartid_map(cpuid); > + unsigned long hartid = cpuid_to_hartid_map(cpuid); > > rc = sbi_hsm_hart_get_status(hartid); > > -- > 2.25.1 > Reviewed-by: Atish Patra -- Regards, Atish From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4CD88C433FE for ; Thu, 26 May 2022 22:54:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 26 May 2022 15:54:33 -0700 (PDT) MIME-Version: 1.0 References: <20220526101131.2340729-1-sunilvl@ventanamicro.com> <20220526101131.2340729-2-sunilvl@ventanamicro.com> In-Reply-To: <20220526101131.2340729-2-sunilvl@ventanamicro.com> From: Atish Patra Date: Thu, 26 May 2022 15:54:22 -0700 Message-ID: Subject: Re: [PATCH V2 1/5] riscv: cpu_ops_sbi: Support for 64bit hartid To: Sunil V L Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel , linux-riscv , "linux-kernel@vger.kernel.org List" , linux-efi , Sunil V L X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220526_155435_341940_BEE14699 X-CRM114-Status: GOOD ( 16.59 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, May 26, 2022 at 3:11 AM Sunil V L wrote: > > The hartid can be a 64bit value on RV64 platforms. This patch modifies > the hartid variable type to unsigned long so that it can hold 64bit > value on RV64 platforms. > > Signed-off-by: Sunil V L > Reviewed-by: Heinrich Schuchardt > --- > arch/riscv/kernel/cpu_ops_sbi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sbi.c > index 4f5a6f84e2a4..efa0f0816634 100644 > --- a/arch/riscv/kernel/cpu_ops_sbi.c > +++ b/arch/riscv/kernel/cpu_ops_sbi.c > @@ -65,7 +65,7 @@ static int sbi_hsm_hart_get_status(unsigned long hartid) > static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle) > { > unsigned long boot_addr = __pa_symbol(secondary_start_sbi); > - int hartid = cpuid_to_hartid_map(cpuid); > + unsigned long hartid = cpuid_to_hartid_map(cpuid); > unsigned long hsm_data; > struct sbi_hart_boot_data *bdata = &per_cpu(boot_data, cpuid); > > @@ -107,7 +107,7 @@ static void sbi_cpu_stop(void) > static int sbi_cpu_is_stopped(unsigned int cpuid) > { > int rc; > - int hartid = cpuid_to_hartid_map(cpuid); > + unsigned long hartid = cpuid_to_hartid_map(cpuid); > > rc = sbi_hsm_hart_get_status(hartid); > > -- > 2.25.1 > Reviewed-by: Atish Patra -- Regards, Atish _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv