From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D6D8C43334 for ; Mon, 27 Jun 2022 07:04:41 +0000 (UTC) Received: from localhost ([::1]:44488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o5inY-0006UU-5I for qemu-devel@archiver.kernel.org; Mon, 27 Jun 2022 03:04:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50374) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o5ikz-0005Ce-R8 for qemu-devel@nongnu.org; Mon, 27 Jun 2022 03:02:01 -0400 Received: from mail-yb1-xb29.google.com ([2607:f8b0:4864:20::b29]:39873) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o5iku-0000hE-Bw for qemu-devel@nongnu.org; Mon, 27 Jun 2022 03:02:01 -0400 Received: by mail-yb1-xb29.google.com with SMTP id r3so15153178ybr.6 for ; Mon, 27 Jun 2022 00:01:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atishpatra.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=aLN80trak9GFXzASdT2oj/4CVlTYZPUHoQzGhAMByUk=; b=V9XmOoW4JzkzAHetbiR+2NA0+034A8ab7qOg554mw47KLh3H6x71fwzvDoO862ihRw 7peIt2788i+aruPrndyMneij3wA30lgGpmJ/cHgxbWz/e93ISRDdguYIXnswYwrC1kUz BnG5eumZxcn298ZRT0IDO5svS6dwentwzqGKw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=aLN80trak9GFXzASdT2oj/4CVlTYZPUHoQzGhAMByUk=; b=KbDB428JnqrfnIu5KjsFhP/AyD5GHlnHZnsiE03/1vCMbzhtV2MFhxBNYXfuYnQDYH X89OvA+H4hh3cHLbVPk5EJbHdmVNJ+suAN6+BeOU9sYf/xFunpHwcGyb7hoJespkGj78 RX8uhtZtqovzKmeWtq2qwdW3LMJrlds5/PClGe38IT4EgvO8DJAB9iUmomt7ieXbgTVQ +DViuIbKJPId82KBqQSpubyNb01FIS1L7VQxxSjXMJT06teApIpGvHmU6Rq0rnCYHwH0 6nLBNYbRuUNfKL3O5HXseK2Bq2W20STCmsEveb7+5df6yztufdHSu43+e3lwY8lwEzeS RhHw== X-Gm-Message-State: AJIora/+fsen4zV7ZHJGyg4VxkctuMd0zf6mlG82yr14fLoO3MHwu02+ wiNo8aMvFOg5lw/ZJJIlsYP3/S8RLDEzr2d0nOkD X-Google-Smtp-Source: AGRyM1uV35/WYmS989DInmu/6VT4x6G6Ovlu6YKOG2Vf5kMmmMCNIIAk/hh+t/cNOjwBEcLysWsqJveLvBo36USkT9I= X-Received: by 2002:a05:6902:136c:b0:649:81aa:5f7b with SMTP id bt12-20020a056902136c00b0064981aa5f7bmr11983455ybb.303.1656313314777; Mon, 27 Jun 2022 00:01:54 -0700 (PDT) MIME-Version: 1.0 References: <20220608062015.317894-1-alistair.francis@opensource.wdc.com> In-Reply-To: <20220608062015.317894-1-alistair.francis@opensource.wdc.com> From: Atish Patra Date: Mon, 27 Jun 2022 00:01:44 -0700 Message-ID: Subject: Re: [PATCH] hw/riscv: boot: Reduce FDT address alignment constraints To: Alistair Francis Cc: "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , Bin Meng , Alistair Francis , Palmer Dabbelt , Bin Meng , Alistair Francis Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::b29; envelope-from=atishp@atishpatra.org; helo=mail-yb1-xb29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Jun 7, 2022 at 11:21 PM Alistair Francis wrote: > > From: Alistair Francis > > We previously stored the device tree at a 16MB alignment from the end of > memory (or 3GB). This means we need at least 16MB of memory to be able > to do this. We don't actually need the FDT to be 16MB aligned, so let's > drop it down to 2MB so that we can support systems with less memory, > while also allowing FDT size expansion. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/992 > Signed-off-by: Alistair Francis > --- > hw/riscv/boot.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 57a41df8e9..e476d8f491 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -226,11 +226,11 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > /* > * We should put fdt as far as possible to avoid kernel/initrd overwriting > * its content. But it should be addressable by 32 bit system as well. > - * Thus, put it at an 16MB aligned address that less than fdt size from the > + * Thus, put it at an 2MB aligned address that less than fdt size from the > * end of dram or 3GB whichever is lesser. > */ > temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; > - fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB); > + fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); > > ret = fdt_pack(fdt); > /* Should only fail if we've built a corrupted tree */ > -- > 2.36.1 > > Reviewed-by: Atish Patra -- Regards, Atish