From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 910AEC433F5 for ; Mon, 9 May 2022 19:14:34 +0000 (UTC) Received: from localhost ([::1]:56882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no8q1-0002oE-Du for qemu-devel@archiver.kernel.org; Mon, 09 May 2022 15:14:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35490) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no8op-0001yG-Vm for qemu-devel@nongnu.org; Mon, 09 May 2022 15:13:20 -0400 Received: from mail-yb1-xb29.google.com ([2607:f8b0:4864:20::b29]:34360) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no8oo-0007Mb-3k for qemu-devel@nongnu.org; Mon, 09 May 2022 15:13:19 -0400 Received: by mail-yb1-xb29.google.com with SMTP id y76so26750082ybe.1 for ; Mon, 09 May 2022 12:13:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atishpatra.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=9OqDkRRuvVTI2G4Jm93FQeyym7FQ71vx2PHKq8by+Ec=; b=KHE5KQLNvafD44CEMDsiNMDsvYWIRRWfVphhc0+lDgb8Qy5K0cF4IVnjwcOC7HA/D4 UCaNRTA29U0pZbrrD9wcaj28/ldj7w2Zx2GfydUt4FyruIj4ab6TGMfQddYGCkAODIR2 LP4K63ubYwKliqTXrwZzuQBn5pp54vhl9u0F8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=9OqDkRRuvVTI2G4Jm93FQeyym7FQ71vx2PHKq8by+Ec=; b=3veIUG66F8x7g0U+iyEiHUgBGeqNoQ+UlKCWBrbFX2vaGu5lkQuSqP9qFDR4VkT54X d/mYI2HATTQw2RVfLYjsRTS8E+bGnxtNida5XKHqX5SY2HnXbMHt+COsTLGTK3k0wYR4 GyhnbA6l8tWbhaqhneLEMFwYeop2JGh3DLPjD0oa7rHA2wsXRKkKI6qnVhQqMKhuc071 spTe3o1oIG/Maqbmxr+A3i7vj7ywhGl23oe68xlXT38GP2m6DsfpoaGbFr9Kkgka64W+ ZpoCx8GY2uw1r4B5r9u9+GJemQ1w/s+CVSuqsBfm4pq34cRzRNWVAEVuuDglTgb468Nb bbYg== X-Gm-Message-State: AOAM5313JXZKhbyYcXmfGiDRbsn5lr3Uwx1StiEetWnQaJnl1loYtaSZ OvpnFQchJfZVxHhH+n3HnBamm2/YqqHThPb1OKSP X-Google-Smtp-Source: ABdhPJyj1OFDeJa7TiMWgT4Meg7t7pqee5ERU/Wh12DXlpMQYSa+6a0xU+vXKPjJfOISKc2tLy9MA5OI3LFeoZN9r38= X-Received: by 2002:a25:9247:0:b0:645:ddd5:a182 with SMTP id e7-20020a259247000000b00645ddd5a182mr14460943ybo.289.1652123596522; Mon, 09 May 2022 12:13:16 -0700 (PDT) MIME-Version: 1.0 References: <20220429033409.258707-1-apatel@ventanamicro.com> <20220429033409.258707-2-apatel@ventanamicro.com> In-Reply-To: From: Atish Patra Date: Mon, 9 May 2022 12:13:05 -0700 Message-ID: Subject: Re: [PATCH 1/4] target/riscv: Fix csr number based privilege checking To: Frank Chang Cc: Anup Patel , Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Anup Patel , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" Content-Type: multipart/alternative; boundary="000000000000189ccd05de9900d5" Received-SPF: pass client-ip=2607:f8b0:4864:20::b29; envelope-from=atishp@atishpatra.org; helo=mail-yb1-xb29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000189ccd05de9900d5 Content-Type: text/plain; charset="UTF-8" On Fri, Apr 29, 2022 at 8:20 PM Frank Chang wrote: > Reviewed-by: Frank Chang > > On Fri, Apr 29, 2022 at 11:34 AM Anup Patel > wrote: > >> When hypervisor and VS CSRs are accessed from VS-mode or VU-mode, >> the riscv_csrrw_check() function should generate virtual instruction >> trap instead illegal instruction trap. >> >> Fixes: 533c91e8f22c ("target/riscv: Use RISCVException enum for >> CSR access") >> > This is not the correct Fixes tag. This patch just changed the error code to enum. The above said issue exists before this patch. I think the correct fix should be 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode"). No ? > Signed-off-by: Anup Patel >> --- >> target/riscv/csr.c | 8 ++++++-- >> 1 file changed, 6 insertions(+), 2 deletions(-) >> >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >> index 3500e07f92..2bf0a97196 100644 >> --- a/target/riscv/csr.c >> +++ b/target/riscv/csr.c >> @@ -3139,7 +3139,7 @@ static inline RISCVException >> riscv_csrrw_check(CPURISCVState *env, >> int read_only = get_field(csrno, 0xC00) == 3; >> int csr_min_priv = csr_ops[csrno].min_priv_ver; >> #if !defined(CONFIG_USER_ONLY) >> - int effective_priv = env->priv; >> + int csr_priv, effective_priv = env->priv; >> >> if (riscv_has_ext(env, RVH) && >> env->priv == PRV_S && >> @@ -3152,7 +3152,11 @@ static inline RISCVException >> riscv_csrrw_check(CPURISCVState *env, >> effective_priv++; >> } >> >> - if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { >> + csr_priv = get_field(csrno, 0x300); >> + if (!env->debugger && (effective_priv < csr_priv)) { >> + if (csr_priv == (PRV_S + 1) && riscv_cpu_virt_enabled(env)) { >> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; >> + } >> return RISCV_EXCP_ILLEGAL_INST; >> } >> #endif >> -- >> 2.34.1 >> >> >> -- Regards, Atish --000000000000189ccd05de9900d5 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Fri, Apr 29, 2022 at 8:20 PM Frank= Chang <frank.chang@sifive.com= > wrote:
=
Reviewed-by: Frank Chang <frank.chang@sifive.com&g= t;

On Fri, Apr 29, 2022 at 11:34 AM Anup Patel <apatel@ventanamicro.com> wrote:<= br>
When hypervisor = and VS CSRs are accessed from VS-mode or VU-mode,
the riscv_csrrw_check() function should generate virtual instruction
trap instead illegal instruction trap.

Fixes: 533c91e8f22c ("target/riscv: Use RISCVException enum for
CSR access")

<= div>This is not the correct Fixes tag. This patch just changed the error co= de to enum.
The above said issue exists before this patch.
I think the correct fix should be=C2=A00a42f4c44088 (" tar= get/riscv: Fix CSR perm checking for HS mode"). No ?
=C2=A0<= /div>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
=C2=A0target/riscv/csr.c | 8 ++++++--
=C2=A01 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3500e07f92..2bf0a97196 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3139,7 +3139,7 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env,
=C2=A0 =C2=A0 =C2=A0int read_only =3D get_field(csrno, 0xC00) =3D=3D 3;
=C2=A0 =C2=A0 =C2=A0int csr_min_priv =3D csr_ops[csrno].min_priv_ver;
=C2=A0#if !defined(CONFIG_USER_ONLY)
-=C2=A0 =C2=A0 int effective_priv =3D env->priv;
+=C2=A0 =C2=A0 int csr_priv, effective_priv =3D env->priv;

=C2=A0 =C2=A0 =C2=A0if (riscv_has_ext(env, RVH) &&
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->priv =3D=3D PRV_S &&
@@ -3152,7 +3152,11 @@ static inline RISCVException riscv_csrrw_check(CPURI= SCVState *env,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0effective_priv++;
=C2=A0 =C2=A0 =C2=A0}

-=C2=A0 =C2=A0 if (!env->debugger && (effective_priv < get_fi= eld(csrno, 0x300))) {
+=C2=A0 =C2=A0 csr_priv =3D get_field(csrno, 0x300);
+=C2=A0 =C2=A0 if (!env->debugger && (effective_priv < csr_pr= iv)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (csr_priv =3D=3D (PRV_S + 1) && ris= cv_cpu_virt_enabled(env)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return RISCV_EXCP_VIRT_INSTRUCTI= ON_FAULT;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return RISCV_EXCP_ILLEGAL_INST;
=C2=A0 =C2=A0 =C2=A0}
=C2=A0#endif
--
2.34.1




--
Regards,
Atish
<= /div>
--000000000000189ccd05de9900d5--