From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41673C433F5 for ; Wed, 25 May 2022 23:50:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345380AbiEYXuA (ORCPT ); Wed, 25 May 2022 19:50:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345082AbiEYXt6 (ORCPT ); Wed, 25 May 2022 19:49:58 -0400 Received: from mail-yb1-xb2c.google.com (mail-yb1-xb2c.google.com [IPv6:2607:f8b0:4864:20::b2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4D536BFDF for ; Wed, 25 May 2022 16:49:57 -0700 (PDT) Received: by mail-yb1-xb2c.google.com with SMTP id p190so353893ybg.4 for ; Wed, 25 May 2022 16:49:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atishpatra.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=2b8MlsVgy0PXNmTV8dy+TKz5ObSmm8PiUnaznemS1Kk=; b=RnE0k5m41tRreeyjV9rIBQp9IS8n51q9BWAAP9GOOssrHJTyMFtm4+pWqy0RYQfjxn yKed2IVryFnIF5xIWCU9MAdGEa/N9nXMxd6lVgHwZeq/y89d3yGfxFLVc3P7CG36Zp4Z KjivNcINMRfMiq3+Hz52iMRYUSqaAgCxB5S/Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=2b8MlsVgy0PXNmTV8dy+TKz5ObSmm8PiUnaznemS1Kk=; b=7bGKk0mexbC7Bs5o/02UE8SKdgiMmx0Vru3PQ6YbJ6ae+dsx6bFNqAGiOFx982+g3M yu2lRxzX7zVn7DCxehG+mB0GBEnhpFZyhgKV6I7QDu3JCZyv9GNly8iraC1FIljwLKIf GW1XlsTQxkR+RJdFxN4qqznd4ep8mJTJZAc7uMkaukdEtGIYnekQqZbT+vrNVKQ9n7IA KMVleuPIfXJXyVeNja2GJ1N/VzeZAehw12FxU6ABfqzCLAa6mfZQApAu+eOu1x6LZJB5 7wNKCYWzfvkswUeRn+56wWQKEl14gkxa0jH3hJOG+wWAX07HCJnLk/+t3XmeFtA6hIuS 8SNQ== X-Gm-Message-State: AOAM53046sbuEKW8Loc0xklmP/p6FJLI2tW/QOSmTpSL7PzrsrPMa+bg 4/aXHy3qHRwHq1OOYpSV6piA3ijF60UMQafMDA9w X-Google-Smtp-Source: ABdhPJx01HOcesLXja2nXoz3VGaZoBMY86NiLV8f653GkRtUx7ztDYWr3KTWHpdFIcaTk74gwDVwL9zVZHwKKB5bmIk= X-Received: by 2002:a25:a287:0:b0:656:29f4:b0c1 with SMTP id c7-20020a25a287000000b0065629f4b0c1mr3996630ybi.598.1653522597025; Wed, 25 May 2022 16:49:57 -0700 (PDT) MIME-Version: 1.0 References: <20220525151106.2176147-1-sunilvl@ventanamicro.com> <20220525151106.2176147-6-sunilvl@ventanamicro.com> <1e90b15b-8c73-0de8-2885-1292923b7575@canonical.com> <5829932A-6E45-46CA-AADA-14EDD903C4AD@jrtc27.com> In-Reply-To: <5829932A-6E45-46CA-AADA-14EDD903C4AD@jrtc27.com> From: Atish Patra Date: Wed, 25 May 2022 16:49:46 -0700 Message-ID: Subject: Re: [PATCH 5/5] riscv/efi_stub: Support for 64bit boot-hartid To: Jessica Clarke Cc: Heinrich Schuchardt , Ard Biesheuvel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Atish Patra , Anup Patel , linux-riscv , Linux Kernel Mailing List , linux-efi , Sunil V L , Sunil V L Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 25, 2022 at 4:36 PM Jessica Clarke wrote: > > On 26 May 2022, at 00:11, Atish Patra wrote: > > > > On Wed, May 25, 2022 at 9:09 AM Heinrich Schuchardt > > wrote: > >> > >> On 5/25/22 17:48, Ard Biesheuvel wrote: > >>> On Wed, 25 May 2022 at 17:11, Sunil V L wrote: > >>>> > >>>> The boot-hartid can be a 64bit value on RV64 platforms. Currently, > >>>> the "boot-hartid" in DT is assumed to be 32bit only. This patch > >>>> detects the size of the "boot-hartid" and uses 32bit or 64bit > >>>> FDT reads appropriately. > >>>> > >>>> Signed-off-by: Sunil V L > >>>> --- > >>>> drivers/firmware/efi/libstub/riscv-stub.c | 12 +++++++++--- > >>>> 1 file changed, 9 insertions(+), 3 deletions(-) > >>>> > >>>> diff --git a/drivers/firmware/efi/libstub/riscv-stub.c b/drivers/firmware/efi/libstub/riscv-stub.c > >>>> index 9e85e58d1f27..d748533f1329 100644 > >>>> --- a/drivers/firmware/efi/libstub/riscv-stub.c > >>>> +++ b/drivers/firmware/efi/libstub/riscv-stub.c > >>>> @@ -29,7 +29,7 @@ static int get_boot_hartid_from_fdt(void) > >>>> { > >>>> const void *fdt; > >>>> int chosen_node, len; > >>>> - const fdt32_t *prop; > >>>> + const void *prop; > >>>> > >>>> fdt = get_efi_config_table(DEVICE_TREE_GUID); > >>>> if (!fdt) > >>>> @@ -40,10 +40,16 @@ static int get_boot_hartid_from_fdt(void) > >>>> return -EINVAL; > >>>> > >>>> prop = fdt_getprop((void *)fdt, chosen_node, "boot-hartid", &len); > >>>> - if (!prop || len != sizeof(u32)) > >>>> + if (!prop) > >>>> + return -EINVAL; > >>>> + > >>>> + if (len == sizeof(u32)) > >>>> + hartid = (unsigned long) fdt32_to_cpu(*(fdt32_t *)prop); > >>>> + else if (len == sizeof(u64)) > >>>> + hartid = (unsigned long) fdt64_to_cpu(*(fdt64_t *)prop); > >>> > >>> Does RISC-V care about alignment? A 64-bit quantity is not guaranteed > >>> to appear 64-bit aligned in the DT, and the cast violates C alignment > >>> rules, so this should probably used get_unaligned_be64() or something > >>> like that. > >> > >> When running in S-mode the SBI handles unaligned access but this has a > >> performance penalty. > >> > >> We could use fdt64_to_cpu(__get_unaligned_t(fdt64_t, prop)) here. > >> > > > > It is better to avoid unaligned access in the kernel. There are some > > plans to disable > > misaligned load/store emulation in the firmware if user space requests > > it via prctl. > > Why? > To support prctl call with PR_SET_UNALIGN > Jess > > > We need another SBI extension to do that. The idea is to keep it > > enabled by default in the firmware but > > userspace should have an option to disable it via prctl. If we make > > sure that the kernel doesn't invoke any > > unaligned access, this feature can be implemented easily. > > > >> Best regards > >> > >> Heinrich > >> > >>> > >>> > >>>> + else > >>>> return -EINVAL; > >>>> > >>>> - hartid = fdt32_to_cpu(*prop); > >>>> return 0; > >>>> } > >>>> > >>>> -- > >>>> 2.25.1 > >>>> > >> > > > > > > -- > > Regards, > > Atish > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > -- Regards, Atish From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3639BC433EF for ; Wed, 25 May 2022 23:50:12 +0000 (UTC) DKIM-Signature: v=1; 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Wed, 25 May 2022 16:49:57 -0700 (PDT) MIME-Version: 1.0 References: <20220525151106.2176147-1-sunilvl@ventanamicro.com> <20220525151106.2176147-6-sunilvl@ventanamicro.com> <1e90b15b-8c73-0de8-2885-1292923b7575@canonical.com> <5829932A-6E45-46CA-AADA-14EDD903C4AD@jrtc27.com> In-Reply-To: <5829932A-6E45-46CA-AADA-14EDD903C4AD@jrtc27.com> From: Atish Patra Date: Wed, 25 May 2022 16:49:46 -0700 Message-ID: Subject: Re: [PATCH 5/5] riscv/efi_stub: Support for 64bit boot-hartid To: Jessica Clarke Cc: Heinrich Schuchardt , Ard Biesheuvel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Atish Patra , Anup Patel , linux-riscv , Linux Kernel Mailing List , linux-efi , Sunil V L , Sunil V L X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220525_164958_356093_E6F29A53 X-CRM114-Status: GOOD ( 35.12 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, May 25, 2022 at 4:36 PM Jessica Clarke wrote: > > On 26 May 2022, at 00:11, Atish Patra wrote: > > > > On Wed, May 25, 2022 at 9:09 AM Heinrich Schuchardt > > wrote: > >> > >> On 5/25/22 17:48, Ard Biesheuvel wrote: > >>> On Wed, 25 May 2022 at 17:11, Sunil V L wrote: > >>>> > >>>> The boot-hartid can be a 64bit value on RV64 platforms. Currently, > >>>> the "boot-hartid" in DT is assumed to be 32bit only. This patch > >>>> detects the size of the "boot-hartid" and uses 32bit or 64bit > >>>> FDT reads appropriately. > >>>> > >>>> Signed-off-by: Sunil V L > >>>> --- > >>>> drivers/firmware/efi/libstub/riscv-stub.c | 12 +++++++++--- > >>>> 1 file changed, 9 insertions(+), 3 deletions(-) > >>>> > >>>> diff --git a/drivers/firmware/efi/libstub/riscv-stub.c b/drivers/firmware/efi/libstub/riscv-stub.c > >>>> index 9e85e58d1f27..d748533f1329 100644 > >>>> --- a/drivers/firmware/efi/libstub/riscv-stub.c > >>>> +++ b/drivers/firmware/efi/libstub/riscv-stub.c > >>>> @@ -29,7 +29,7 @@ static int get_boot_hartid_from_fdt(void) > >>>> { > >>>> const void *fdt; > >>>> int chosen_node, len; > >>>> - const fdt32_t *prop; > >>>> + const void *prop; > >>>> > >>>> fdt = get_efi_config_table(DEVICE_TREE_GUID); > >>>> if (!fdt) > >>>> @@ -40,10 +40,16 @@ static int get_boot_hartid_from_fdt(void) > >>>> return -EINVAL; > >>>> > >>>> prop = fdt_getprop((void *)fdt, chosen_node, "boot-hartid", &len); > >>>> - if (!prop || len != sizeof(u32)) > >>>> + if (!prop) > >>>> + return -EINVAL; > >>>> + > >>>> + if (len == sizeof(u32)) > >>>> + hartid = (unsigned long) fdt32_to_cpu(*(fdt32_t *)prop); > >>>> + else if (len == sizeof(u64)) > >>>> + hartid = (unsigned long) fdt64_to_cpu(*(fdt64_t *)prop); > >>> > >>> Does RISC-V care about alignment? A 64-bit quantity is not guaranteed > >>> to appear 64-bit aligned in the DT, and the cast violates C alignment > >>> rules, so this should probably used get_unaligned_be64() or something > >>> like that. > >> > >> When running in S-mode the SBI handles unaligned access but this has a > >> performance penalty. > >> > >> We could use fdt64_to_cpu(__get_unaligned_t(fdt64_t, prop)) here. > >> > > > > It is better to avoid unaligned access in the kernel. There are some > > plans to disable > > misaligned load/store emulation in the firmware if user space requests > > it via prctl. > > Why? > To support prctl call with PR_SET_UNALIGN > Jess > > > We need another SBI extension to do that. The idea is to keep it > > enabled by default in the firmware but > > userspace should have an option to disable it via prctl. If we make > > sure that the kernel doesn't invoke any > > unaligned access, this feature can be implemented easily. > > > >> Best regards > >> > >> Heinrich > >> > >>> > >>> > >>>> + else > >>>> return -EINVAL; > >>>> > >>>> - hartid = fdt32_to_cpu(*prop); > >>>> return 0; > >>>> } > >>>> > >>>> -- > >>>> 2.25.1 > >>>> > >> > > > > > > -- > > Regards, > > Atish > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > -- Regards, Atish _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv