From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F1A9C43334 for ; Wed, 6 Jul 2022 21:38:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234382AbiGFViP (ORCPT ); Wed, 6 Jul 2022 17:38:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234001AbiGFViO (ORCPT ); Wed, 6 Jul 2022 17:38:14 -0400 Received: from mail-yw1-x1133.google.com (mail-yw1-x1133.google.com [IPv6:2607:f8b0:4864:20::1133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79CFCE8C for ; Wed, 6 Jul 2022 14:38:13 -0700 (PDT) Received: by mail-yw1-x1133.google.com with SMTP id 00721157ae682-31c89111f23so102709487b3.0 for ; Wed, 06 Jul 2022 14:38:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atishpatra.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=YMOUx8tRXrNtuUeXMdx6sLrOQrLpo6dcTRjSCKuQc0Y=; b=UYKAelmyu8hR8xtMcdAR5kd1mv8eoTvSrr43mXrkLTDNp7Up1QaEHT06vXLI2hfzGi UgyOvRNXV+lnTdsGajUy0ju4uTNazHUOkRkqbgyEg9cM3N8iAYjp4BSKrQMLIxcIPNF8 jCzJvOSiH9aVkes4u0/X29QTr5+jvw3j86MAY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=YMOUx8tRXrNtuUeXMdx6sLrOQrLpo6dcTRjSCKuQc0Y=; b=h7ZtqobUvU2B2VDWA8at3E9hZm+xyeFXRWixm0rmct1rsEF24Di30mzx2Jg6haGtLH WaqxP1DhvFOypkUeQzArhD5Jh48ry25cwcVU/75Wa79V1ZsH0o4/VAj6HpHMLM6lDAS1 e+48FxXgjvuPRsp5PUNUUzW2Hz/BojyI7DK77IUs87Ow6BMbzAjwnGO2QtwsfIbrzEmj KZUO6ddI2gSDtAUfv6wuFh0WBwTgQfjNe9OiI4Qa8qy+uoJv/DpQJFEp9zE3sxDgd2zG efieu85k7axrHNKTp/OICNXKGfW/SZWGAdAzmyKe9NDjHRf6kYWZ0IPDXwhI3DDUQSAm C/ZQ== X-Gm-Message-State: AJIora/qCKAOhBSrFIFP2XZbjE+Ch0FelQqdXAfBmqS6qFFjLqxuTWZ2 4hyPLLaaiqqcQ57dSHp+EZGhX37eUkq4L8HS1k3Z X-Google-Smtp-Source: AGRyM1sNTMRWdcWaAn/JcWOrEElU7WU313tb8SJ6Kx2VtTNjPmBkJmDIQgRho/GXT0d2qFVlZcIMuFkHuyG4GfG7DBs= X-Received: by 2002:a81:5d55:0:b0:31c:dce7:96c9 with SMTP id r82-20020a815d55000000b0031cdce796c9mr9652700ywb.519.1657143492665; Wed, 06 Jul 2022 14:38:12 -0700 (PDT) MIME-Version: 1.0 References: <20220706184558.2557301-1-mail@conchuod.ie> In-Reply-To: <20220706184558.2557301-1-mail@conchuod.ie> From: Atish Patra Date: Wed, 6 Jul 2022 14:38:01 -0700 Message-ID: Subject: Re: [PATCH] riscv: arch-topology: fix default topology reporting To: Conor Dooley Cc: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Sudeep Holla , Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld , Guo Ren , Anup Patel , Changbin Du , Heiko Stuebner , Philipp Tomsich , linux-riscv , "linux-kernel@vger.kernel.org List" , Brice Goglin Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 6, 2022 at 11:46 AM Conor Dooley wrote: > > From: Conor Dooley > > RISC-V has no sane defaults to fall back on where there is no cpu-map > in the devicetree. > Without sane defaults, the package, core and thread IDs are all set to > -1. This causes user-visible inaccuracies for tools like hwloc/lstopo > which rely on the sysfs cpu topology files to detect a system's > topology. > > Add sane defaults in ~the exact same way as ARM64. > > CC: stable@vger.kernel.org > Fixes: 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") > Reported-by: Brice Goglin > Link: https://github.com/open-mpi/hwloc/issues/536 > Signed-off-by: Conor Dooley > --- > > Sudeep suggested that this be backported rather than the changes to > the devicetrees adding cpu-map since that property is optional. > That patchset is still valid in it's own right. > > arch/riscv/include/asm/topology.h | 13 +++++++++++++ > arch/riscv/kernel/Makefile | 1 + > arch/riscv/kernel/smpboot.c | 4 ++++ > arch/riscv/kernel/topology.c | 32 +++++++++++++++++++++++++++++++ > 4 files changed, 50 insertions(+) > create mode 100644 arch/riscv/include/asm/topology.h > create mode 100644 arch/riscv/kernel/topology.c > > diff --git a/arch/riscv/include/asm/topology.h b/arch/riscv/include/asm/topology.h > new file mode 100644 > index 000000000000..36bc6ecda898 > --- /dev/null > +++ b/arch/riscv/include/asm/topology.h > @@ -0,0 +1,13 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries > + */ > + > +#ifndef _ASM_RISCV_TOPOLOGY_H > +#define _ASM_RISCV_TOPOLOGY_H > + > +#include > + > +void store_cpu_topology(unsigned int cpuid); > + > +#endif /* _ASM_RISCV_TOPOLOGY_H */ > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile > index c71d6591d539..9518882ba6f9 100644 > --- a/arch/riscv/kernel/Makefile > +++ b/arch/riscv/kernel/Makefile > @@ -50,6 +50,7 @@ obj-y += riscv_ksyms.o > obj-y += stacktrace.o > obj-y += cacheinfo.o > obj-y += patch.o > +obj-y += topology.o > obj-y += probes/ > obj-$(CONFIG_MMU) += vdso.o vdso/ > > diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c > index f1e4948a4b52..d551c7f452d4 100644 > --- a/arch/riscv/kernel/smpboot.c > +++ b/arch/riscv/kernel/smpboot.c > @@ -32,6 +32,7 @@ > #include > #include > #include > +#include > > #include "head.h" > > @@ -40,6 +41,8 @@ static DECLARE_COMPLETION(cpu_running); > void __init smp_prepare_boot_cpu(void) > { > init_cpu_topology(); > + > + store_cpu_topology(smp_processor_id()); > } > > void __init smp_prepare_cpus(unsigned int max_cpus) > @@ -161,6 +164,7 @@ asmlinkage __visible void smp_callin(void) > mmgrab(mm); > current->active_mm = mm; > > + store_cpu_topology(curr_cpuid); > notify_cpu_starting(curr_cpuid); > numa_add_cpu(curr_cpuid); > update_siblings_masks(curr_cpuid); > diff --git a/arch/riscv/kernel/topology.c b/arch/riscv/kernel/topology.c > new file mode 100644 > index 000000000000..db72862bd5b5 > --- /dev/null > +++ b/arch/riscv/kernel/topology.c > @@ -0,0 +1,32 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries > + * > + * Based on the arm64 version, which was in turn based on arm32, which was > + * ultimately based on sh's. > + * The arm64 version was listed as: > + * Copyright (C) 2011,2013,2014 Linaro Limited. > + */ > + > +#include > +#include > +#include > + > +void store_cpu_topology(unsigned int cpuid) > +{ > + struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; > + > + if (cpuid_topo->package_id != -1) > + goto topology_populated; > + > + cpuid_topo->thread_id = -1; > + cpuid_topo->core_id = cpuid; > + cpuid_topo->package_id = cpu_to_node(cpuid); > + > + pr_debug("CPU%u: package %d core %d thread %d\n", > + cpuid, cpuid_topo->package_id, cpuid_topo->core_id, > + cpuid_topo->thread_id); > + > +topology_populated: > + update_siblings_masks(cpuid); > +} > This function is pretty much the same as the arm64 one except the UP/mpidr check. Can we move this to the common code as well ? > base-commit: b6f1f2fa2bddd69ff46a190b8120bd440fd50563 > -- > 2.37.0 > -- Regards, Atish From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C63A3C433EF for ; Wed, 6 Jul 2022 21:38:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=46GkCjGW5ldthLCmbKZgzwFQlYKXEZ86bc8VZxSHD4I=; b=e2DQP/ceT02Gn9 j8iTd0iT/V+hfPF5SYSrd7d0xHnSvLsMar/c/1xbrjqnkOGYGFAUFE8mGxdpYGAuutH7hI5OV8DKM aXr0+PbbkQiKg/i5q0s4Arm69TcZ200GkSWRFxO7WrpsaL2tcuEVc0lgQXPPJs6HG5rU9NPiAvdaz Bkz/xZAmch/Q6VnLYNapf0EgBha8rEDqIsOPY7/fkPPGZoNM6KRD0wVV1isXEiAGWT733YjYdI/gV sgiK7LaekaDc9ONmqNk0rgXQynAx2fJmCKhveTLQkqPdDIYbR+tVS1MKEzb1F6347JiCo+1cPI0nR l4mHBaGonRf8bP1+pknA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o9Ciz-00CTw4-39; Wed, 06 Jul 2022 21:38:21 +0000 Received: from mail-yw1-x1136.google.com ([2607:f8b0:4864:20::1136]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o9Civ-00CTv2-Kf for linux-riscv@lists.infradead.org; Wed, 06 Jul 2022 21:38:19 +0000 Received: by mail-yw1-x1136.google.com with SMTP id 00721157ae682-31c8a1e9e33so100718997b3.5 for ; Wed, 06 Jul 2022 14:38:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atishpatra.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=YMOUx8tRXrNtuUeXMdx6sLrOQrLpo6dcTRjSCKuQc0Y=; b=UYKAelmyu8hR8xtMcdAR5kd1mv8eoTvSrr43mXrkLTDNp7Up1QaEHT06vXLI2hfzGi UgyOvRNXV+lnTdsGajUy0ju4uTNazHUOkRkqbgyEg9cM3N8iAYjp4BSKrQMLIxcIPNF8 jCzJvOSiH9aVkes4u0/X29QTr5+jvw3j86MAY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=YMOUx8tRXrNtuUeXMdx6sLrOQrLpo6dcTRjSCKuQc0Y=; b=RCKZhYzG+nlqOIWwaktC7/TXM/b0XoNBP7z9i0GfwyQ0kjNhtEgVWKH1etoURzxl80 aCJwtoH9rptsod62ZO4VqLzLVG2dxt7/0o32doitrPB55KBTjK4Uh3yu5kShBEy/ofdT 9M2FlP4NwxGWlgwcTVS6UBEx+/a+R5uMwB02/AIKnflQeB1rndhd9GVx7yzlj1NCQ7Zh 8G/tEcm+t7WiYj/aaUPx+XVcmsKRVu246RYHGRZNTnpe+4mn15bEg4ZO1KMJO1cVP0QG PT4qqP5FkwVgestteplKdraHeZ5RbjrDWE25gao4RtzUUT9iT+WHnWENc+qYTWOT3h3s dUgQ== X-Gm-Message-State: AJIora/fDnJgZHyS0JIJi2GIKTDljTCzbsTDlXUjferQ/wXmOPmlSwjA OqGfrfO5gFqBYiTPbyw8cbC3BHz5i1q4Ppe0TxRH X-Google-Smtp-Source: AGRyM1sNTMRWdcWaAn/JcWOrEElU7WU313tb8SJ6Kx2VtTNjPmBkJmDIQgRho/GXT0d2qFVlZcIMuFkHuyG4GfG7DBs= X-Received: by 2002:a81:5d55:0:b0:31c:dce7:96c9 with SMTP id r82-20020a815d55000000b0031cdce796c9mr9652700ywb.519.1657143492665; Wed, 06 Jul 2022 14:38:12 -0700 (PDT) MIME-Version: 1.0 References: <20220706184558.2557301-1-mail@conchuod.ie> In-Reply-To: <20220706184558.2557301-1-mail@conchuod.ie> From: Atish Patra Date: Wed, 6 Jul 2022 14:38:01 -0700 Message-ID: Subject: Re: [PATCH] riscv: arch-topology: fix default topology reporting To: Conor Dooley Cc: Paul Walmsley , Palmer Dabbelt , Palmer Dabbelt , Albert Ou , Sudeep Holla , Daire McNamara , Conor Dooley , Niklas Cassel , Damien Le Moal , Geert Uytterhoeven , Zong Li , Emil Renner Berthing , Jonas Hahnfeld , Guo Ren , Anup Patel , Changbin Du , Heiko Stuebner , Philipp Tomsich , linux-riscv , "linux-kernel@vger.kernel.org List" , Brice Goglin X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220706_143817_725233_976CD557 X-CRM114-Status: GOOD ( 27.97 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Jul 6, 2022 at 11:46 AM Conor Dooley wrote: > > From: Conor Dooley > > RISC-V has no sane defaults to fall back on where there is no cpu-map > in the devicetree. > Without sane defaults, the package, core and thread IDs are all set to > -1. This causes user-visible inaccuracies for tools like hwloc/lstopo > which rely on the sysfs cpu topology files to detect a system's > topology. > > Add sane defaults in ~the exact same way as ARM64. > > CC: stable@vger.kernel.org > Fixes: 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") > Reported-by: Brice Goglin > Link: https://github.com/open-mpi/hwloc/issues/536 > Signed-off-by: Conor Dooley > --- > > Sudeep suggested that this be backported rather than the changes to > the devicetrees adding cpu-map since that property is optional. > That patchset is still valid in it's own right. > > arch/riscv/include/asm/topology.h | 13 +++++++++++++ > arch/riscv/kernel/Makefile | 1 + > arch/riscv/kernel/smpboot.c | 4 ++++ > arch/riscv/kernel/topology.c | 32 +++++++++++++++++++++++++++++++ > 4 files changed, 50 insertions(+) > create mode 100644 arch/riscv/include/asm/topology.h > create mode 100644 arch/riscv/kernel/topology.c > > diff --git a/arch/riscv/include/asm/topology.h b/arch/riscv/include/asm/topology.h > new file mode 100644 > index 000000000000..36bc6ecda898 > --- /dev/null > +++ b/arch/riscv/include/asm/topology.h > @@ -0,0 +1,13 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries > + */ > + > +#ifndef _ASM_RISCV_TOPOLOGY_H > +#define _ASM_RISCV_TOPOLOGY_H > + > +#include > + > +void store_cpu_topology(unsigned int cpuid); > + > +#endif /* _ASM_RISCV_TOPOLOGY_H */ > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile > index c71d6591d539..9518882ba6f9 100644 > --- a/arch/riscv/kernel/Makefile > +++ b/arch/riscv/kernel/Makefile > @@ -50,6 +50,7 @@ obj-y += riscv_ksyms.o > obj-y += stacktrace.o > obj-y += cacheinfo.o > obj-y += patch.o > +obj-y += topology.o > obj-y += probes/ > obj-$(CONFIG_MMU) += vdso.o vdso/ > > diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c > index f1e4948a4b52..d551c7f452d4 100644 > --- a/arch/riscv/kernel/smpboot.c > +++ b/arch/riscv/kernel/smpboot.c > @@ -32,6 +32,7 @@ > #include > #include > #include > +#include > > #include "head.h" > > @@ -40,6 +41,8 @@ static DECLARE_COMPLETION(cpu_running); > void __init smp_prepare_boot_cpu(void) > { > init_cpu_topology(); > + > + store_cpu_topology(smp_processor_id()); > } > > void __init smp_prepare_cpus(unsigned int max_cpus) > @@ -161,6 +164,7 @@ asmlinkage __visible void smp_callin(void) > mmgrab(mm); > current->active_mm = mm; > > + store_cpu_topology(curr_cpuid); > notify_cpu_starting(curr_cpuid); > numa_add_cpu(curr_cpuid); > update_siblings_masks(curr_cpuid); > diff --git a/arch/riscv/kernel/topology.c b/arch/riscv/kernel/topology.c > new file mode 100644 > index 000000000000..db72862bd5b5 > --- /dev/null > +++ b/arch/riscv/kernel/topology.c > @@ -0,0 +1,32 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries > + * > + * Based on the arm64 version, which was in turn based on arm32, which was > + * ultimately based on sh's. > + * The arm64 version was listed as: > + * Copyright (C) 2011,2013,2014 Linaro Limited. > + */ > + > +#include > +#include > +#include > + > +void store_cpu_topology(unsigned int cpuid) > +{ > + struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; > + > + if (cpuid_topo->package_id != -1) > + goto topology_populated; > + > + cpuid_topo->thread_id = -1; > + cpuid_topo->core_id = cpuid; > + cpuid_topo->package_id = cpu_to_node(cpuid); > + > + pr_debug("CPU%u: package %d core %d thread %d\n", > + cpuid, cpuid_topo->package_id, cpuid_topo->core_id, > + cpuid_topo->thread_id); > + > +topology_populated: > + update_siblings_masks(cpuid); > +} > This function is pretty much the same as the arm64 one except the UP/mpidr check. Can we move this to the common code as well ? > base-commit: b6f1f2fa2bddd69ff46a190b8120bd440fd50563 > -- > 2.37.0 > -- Regards, Atish _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv