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Fri, 28 Jan 2022 17:29:06 -0800 (PST) MIME-Version: 1.0 References: <20220120200735.2739543-1-atishp@rivosinc.com> <20220120200735.2739543-5-atishp@rivosinc.com> <91dbc7a1-f23f-709b-82e8-10e4c96e4482@iscas.ac.cn> In-Reply-To: <91dbc7a1-f23f-709b-82e8-10e4c96e4482@iscas.ac.cn> From: Atish Patra Date: Fri, 28 Jan 2022 17:28:56 -0800 Message-ID: Subject: Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support To: Weiwei Li Content-Type: multipart/alternative; boundary="0000000000003ae62705d6ae7aec" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::b2e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::b2e; envelope-from=atishp@atishpatra.org; helo=mail-yb1-xb2e.google.com X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Anup Patel , Bin Meng , Atish Patra , "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --0000000000003ae62705d6ae7aec Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Jan 26, 2022 at 12:37 AM Weiwei Li wrote: > > =E5=9C=A8 2022/1/21 =E4=B8=8A=E5=8D=884:07, Atish Patra =E5=86=99=E9=81= =93: > > The RISC-V privileged specification v1.12 defines few execution > > environment configuration CSRs that can be used enable/disable > > extensions per privilege levels. > > > > Add the basic support for these CSRs. > > > > Signed-off-by: Atish Patra > > --- > > target/riscv/cpu.h | 8 ++++ > > target/riscv/cpu_bits.h | 31 +++++++++++++++ > > target/riscv/csr.c | 84 ++++++++++++++++++++++++++++++++++++++++= + > > target/riscv/machine.c | 26 +++++++++++++ > > 4 files changed, 149 insertions(+) > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 7f87917204c5..b9462300a472 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -264,6 +264,14 @@ struct CPURISCVState { > > target_ulong spmbase; > > target_ulong upmmask; > > target_ulong upmbase; > > + > > + /* CSRs for execution enviornment configuration */ > > + > > + target_ulong menvcfg; > > + target_ulong menvcfgh; > > I think we needn't maintain seperate menvcfg and menvcfgh, just use > "uint64_t menvcfg" as the way of mstatus. > > unlike mstatush, menvcfgh/henvcfgh will be accessed directly to do runtime predicate for stimecmp/vstimecmp. We have to do the 32 bit shifting during every check which makes the code hard to read at the cost of 2 ulongs. IMO, having separate variables is much simpler. Similar to henvcfg and henvcfg. > > > + target_ulong senvcfg; > > + target_ulong henvcfg; > > + target_ulong henvcfgh; > > #endif > > > > float_status fp_status; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > index f6f90b5cbd52..afb237c2313b 100644 > > --- a/target/riscv/cpu_bits.h > > +++ b/target/riscv/cpu_bits.h > > @@ -177,6 +177,9 @@ > > #define CSR_STVEC 0x105 > > #define CSR_SCOUNTEREN 0x106 > > > > +/* Supervisor Configuration CSRs */ > > +#define CSR_SENVCFG 0x10A > > + > > /* Supervisor Trap Handling */ > > #define CSR_SSCRATCH 0x140 > > #define CSR_SEPC 0x141 > > @@ -204,6 +207,10 @@ > > #define CSR_HTIMEDELTA 0x605 > > #define CSR_HTIMEDELTAH 0x615 > > > > +/* Hypervisor Configuration CSRs */ > > +#define CSR_HENVCFG 0x60A > > +#define CSR_HENVCFGH 0x61A > > + > > /* Virtual CSRs */ > > #define CSR_VSSTATUS 0x200 > > #define CSR_VSIE 0x204 > > @@ -218,6 +225,10 @@ > > #define CSR_MTINST 0x34a > > #define CSR_MTVAL2 0x34b > > > > +/* Machine Configuration CSRs */ > > +#define CSR_MENVCFG 0x30A > > +#define CSR_MENVCFGH 0x31A > > + > > /* Enhanced Physical Memory Protection (ePMP) */ > > #define CSR_MSECCFG 0x747 > > #define CSR_MSECCFGH 0x757 > > @@ -578,6 +589,26 @@ typedef enum RISCVException { > > #define PM_EXT_CLEAN 0x00000002ULL > > #define PM_EXT_DIRTY 0x00000003ULL > > > > +/* Execution enviornment configuration bits */ > > +#define MENVCFG_FIOM (1 << 0) > > +#define MENVCFG_CBE 0x30000ULL > > +#define MENVCFG_CBCFE (1 << 6) > > +#define MENVCFG_CBZE (1 << 7) > > +#define MENVCFG_PBMTE (1 << 62) > > +#define MENVCFG_STCE (1 << 63) > > + > > +#define SENVCFG_FIOM MENVCFG_FIOM > > +#define SENVCFG_CBE MENVCFG_CBE > > +#define SENVCFG_CBCFE MENVCFG_CBCFE > > +#define SENVCFG_CBZE MENVCFG_CBZE > > + > > +#define HENVCFG_FIOM MENVCFG_FIOM > > +#define HENVCFG_CBE MENVCFG_CBE > > +#define HENVCFG_CBCFE MENVCFG_CBCFE > > +#define HENVCFG_CBZE MENVCFG_CBZE > > +#define HENVCFG_PBMTE MENVCFG_PBMTE > > +#define HENVCFG_STCE MENVCFG_STCE > > + > > /* Offsets for every pair of control bits per each priv level */ > > #define XS_OFFSET 0ULL > > #define U_OFFSET 2ULL > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index e66bf2201857..a4bbae7a1bbd 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -853,6 +853,77 @@ static RISCVException write_mtval(CPURISCVState > *env, int csrno, > > return RISCV_EXCP_NONE; > > } > > > > +/* Execution environment configuration setup */ > > +static RISCVException read_menvcfg(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val =3D env->menvcfg; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_menvcfg(CPURISCVState *env, int csrno, > > + target_ulong val) > > +{ > > + env->menvcfg =3D val; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val =3D env->menvcfgh; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, > > + target_ulong val) > > +{ > > + env->menvcfgh =3D val; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException read_senvcfg(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val =3D env->senvcfg; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_senvcfg(CPURISCVState *env, int csrno, > > + target_ulong val) > > +{ > > + env->senvcfg =3D val; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException read_henvcfg(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val =3D env->henvcfg; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, > > + target_ulong val) > > +{ > > + env->henvcfg =3D val; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val =3D env->henvcfgh; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, > > + target_ulong val) > > +{ > > + env->henvcfgh =3D val; > > + return RISCV_EXCP_NONE; > > +} > > + > > static RISCVException rmw_mip(CPURISCVState *env, int csrno, > > target_ulong *ret_value, > > target_ulong new_value, target_ulong > write_mask) > > @@ -2054,6 +2125,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D= { > > [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval > }, > > [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip > }, > > > > + /* Execution environment configuration */ > > + [CSR_MENVCFG] =3D { "menvcfg", any, read_menvcfg, > write_menvcfg, NULL, > > + NULL, NULL, > PRIV_VERSION_1_12_0}, > > + [CSR_MENVCFGH] =3D { "menvcfgh", any32, read_menvcfgh, > write_menvcfgh, NULL, > > + NULL, NULL, > PRIV_VERSION_1_12_0}, > > + [CSR_SENVCFG] =3D { "senvcfg", smode, read_senvcfg, > write_senvcfg, NULL, > > + NULL, NULL, > PRIV_VERSION_1_12_0}, > > + [CSR_HENVCFG] =3D { "henvcfg", hmode, read_henvcfg, > write_henvcfg, NULL, > > + NULL, NULL, > PRIV_VERSION_1_12_0}, > > + [CSR_HENVCFGH] =3D { "henvcfgh", hmode32, read_henvcfgh, > write_henvcfgh, NULL, > > + NULL, NULL, > PRIV_VERSION_1_12_0}, > > + > > + > Two new lines here. > Fixed it. Thanks. > > /* Supervisor Trap Setup */ > > [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, > write_sstatus, NULL, > > read_sstatus_i128 > }, > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > > index 13b9ab375b95..59479a999b87 100644 > > --- a/target/riscv/machine.c > > +++ b/target/riscv/machine.c > > @@ -185,6 +185,31 @@ static const VMStateDescription vmstate_rv128 =3D = { > > } > > }; > > > > +/* TODO: henvcfg need both hyper_needed & envcfg_needed */ > > +static bool envcfg_needed(void *opaque) > > +{ > > + RISCVCPU *cpu =3D opaque; > > + CPURISCVState *env =3D &cpu->env; > > + > > + return (env->priv_ver >=3D PRIV_VERSION_1_12_0 ? 1 : 0); > > +} > > + > > +static const VMStateDescription vmstate_envcfg =3D { > > + .name =3D "cpu/envcfg", > > + .version_id =3D 1, > > + .minimum_version_id =3D 1, > > + .needed =3D envcfg_needed, > > + .fields =3D (VMStateField[]) { > > + VMSTATE_UINTTL(env.menvcfg, RISCVCPU), > > + VMSTATE_UINTTL(env.menvcfgh, RISCVCPU), > > + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), > > + VMSTATE_UINTTL(env.henvcfg, RISCVCPU), > > + VMSTATE_UINTTL(env.henvcfgh, RISCVCPU), > > + > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > const VMStateDescription vmstate_riscv_cpu =3D { > > .name =3D "cpu", > > .version_id =3D 3, > > @@ -240,6 +265,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { > > &vmstate_vector, > > &vmstate_pointermasking, > > &vmstate_rv128, > > + &vmstate_envcfg, > > NULL > > } > > }; > > Regards, > > Weiwei Li > > > --=20 Regards, Atish --0000000000003ae62705d6ae7aec Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Wed, Jan 26, 2022 at 12:37 AM Weiw= ei Li <liweiwei@iscas.ac.cn&= gt; wrote:

=E5=9C=A8 2022/1/21 =E4=B8=8A=E5=8D=884:07, Atish Patra =E5=86=99=E9=81=93:=
> The RISC-V privileged specification v1.12 defines few execution
> environment configuration CSRs that can be used enable/disable
> extensions per privilege levels.
>
> Add the basic support for these CSRs.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>=C2=A0 =C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 8 ++++
>=C2=A0 =C2=A0target/riscv/cpu_bits.h | 31 +++++++++++++++
>=C2=A0 =C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 | 84 ++++++++++++++= +++++++++++++++++++++++++++
>=C2=A0 =C2=A0target/riscv/machine.c=C2=A0 | 26 +++++++++++++
>=C2=A0 =C2=A04 files changed, 149 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7f87917204c5..b9462300a472 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -264,6 +264,14 @@ struct CPURISCVState {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong spmbase;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong upmmask;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong upmbase;
> +
> +=C2=A0 =C2=A0 /* CSRs for execution enviornment configuration */
> +
> +=C2=A0 =C2=A0 target_ulong menvcfg;
> +=C2=A0 =C2=A0 target_ulong menvcfgh;

I think we needn't maintain seperate menvcfg and menvcfgh, just use "uint64_t menvcfg" as the way of mstatus.


unlike mstatush, menvcfgh/henvcfgh=C2= =A0will be accessed directly to do runtime
predicate for stimecmp= /vstimecmp.
=C2=A0
We have to do the 32 bit shifting during ev= ery check which makes the code hard to read
at the cost of 2 ulon= gs.

IMO, having separate=C2=A0variables is much simpler.

Similar to=C2=A0 henvcfg and henvcfg.

> +=C2=A0 =C2=A0 target_ulong senvcfg;
> +=C2=A0 =C2=A0 target_ulong henvcfg;
> +=C2=A0 =C2=A0 target_ulong henvcfgh;
>=C2=A0 =C2=A0#endif
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0float_status fp_status;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index f6f90b5cbd52..afb237c2313b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -177,6 +177,9 @@
>=C2=A0 =C2=A0#define CSR_STVEC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= 0x105
>=C2=A0 =C2=A0#define CSR_SCOUNTEREN=C2=A0 =C2=A0 =C2=A0 0x106
>=C2=A0 =C2=A0
> +/* Supervisor Configuration CSRs */
> +#define CSR_SENVCFG=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x10A
> +
>=C2=A0 =C2=A0/* Supervisor Trap Handling */
>=C2=A0 =C2=A0#define CSR_SSCRATCH=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x140
>=C2=A0 =C2=A0#define CSR_SEPC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = 0x141
> @@ -204,6 +207,10 @@
>=C2=A0 =C2=A0#define CSR_HTIMEDELTA=C2=A0 =C2=A0 =C2=A0 0x605
>=C2=A0 =C2=A0#define CSR_HTIMEDELTAH=C2=A0 =C2=A0 =C2=A00x615
>=C2=A0 =C2=A0
> +/* Hypervisor Configuration CSRs */
> +#define CSR_HENVCFG=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x60A
> +#define CSR_HENVCFGH=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x61A
> +
>=C2=A0 =C2=A0/* Virtual CSRs */
>=C2=A0 =C2=A0#define CSR_VSSTATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x200
>=C2=A0 =C2=A0#define CSR_VSIE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = 0x204
> @@ -218,6 +225,10 @@
>=C2=A0 =C2=A0#define CSR_MTINST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x34a=
>=C2=A0 =C2=A0#define CSR_MTVAL2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x34b=
>=C2=A0 =C2=A0
> +/* Machine Configuration CSRs */
> +#define CSR_MENVCFG=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x30A
> +#define CSR_MENVCFGH=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x31A
> +
>=C2=A0 =C2=A0/* Enhanced Physical Memory Protection (ePMP) */
>=C2=A0 =C2=A0#define CSR_MSECCFG=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x747=
>=C2=A0 =C2=A0#define CSR_MSECCFGH=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x757
> @@ -578,6 +589,26 @@ typedef enum RISCVException {
>=C2=A0 =C2=A0#define PM_EXT_CLEAN=C2=A0 =C2=A0 0x00000002ULL
>=C2=A0 =C2=A0#define PM_EXT_DIRTY=C2=A0 =C2=A0 0x00000003ULL
>=C2=A0 =C2=A0
> +/* Execution enviornment configuration bits */
> +#define MENVCFG_FIOM=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 0)
> +#define MENVCFG_CBE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x30000ULL
> +#define MENVCFG_CBCFE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 6)
> +#define MENVCFG_CBZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 7)
> +#define MENVCFG_PBMTE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 62)
> +#define MENVCFG_STCE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 63)
> +
> +#define SENVCFG_FIOM=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_FIOM
> +#define SENVCFG_CBE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBE
> +#define SENVCFG_CBCFE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBCFE
> +#define SENVCFG_CBZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_CBZE
> +
> +#define HENVCFG_FIOM=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_FIOM
> +#define HENVCFG_CBE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBE
> +#define HENVCFG_CBCFE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBCFE
> +#define HENVCFG_CBZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_CBZE
> +#define HENVCFG_PBMTE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_PBMTE
> +#define HENVCFG_STCE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_STCE
> +
>=C2=A0 =C2=A0/* Offsets for every pair of control bits per each priv le= vel */
>=C2=A0 =C2=A0#define XS_OFFSET=C2=A0 =C2=A0 0ULL
>=C2=A0 =C2=A0#define U_OFFSET=C2=A0 =C2=A0 =C2=A02ULL
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index e66bf2201857..a4bbae7a1bbd 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -853,6 +853,77 @@ static RISCVException write_mtval(CPURISCVState *= env, int csrno,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0return RISCV_EXCP_NONE;
>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0
> +/* Execution environment configuration setup */
> +static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *val)
> +{
> +=C2=A0 =C2=A0 *val =3D env->menvcfg;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_menvcfg(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong val)
> +{
> +=C2=A0 =C2=A0 env->menvcfg =3D val;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *val)
> +{
> +=C2=A0 =C2=A0 *val =3D env->menvcfgh;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong val)
> +{
> +=C2=A0 =C2=A0 env->menvcfgh =3D val;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *val)
> +{
> +=C2=A0 =C2=A0 *val =3D env->senvcfg;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_senvcfg(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong val)
> +{
> +=C2=A0 =C2=A0 env->senvcfg =3D val;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *val)
> +{
> +=C2=A0 =C2=A0 *val =3D env->henvcfg;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong val)
> +{
> +=C2=A0 =C2=A0 env->henvcfg =3D val;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *val)
> +{
> +=C2=A0 =C2=A0 *val =3D env->henvcfgh;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong val)
> +{
> +=C2=A0 =C2=A0 env->henvcfgh =3D val;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
>=C2=A0 =C2=A0static RISCVException rmw_mip(CPURISCVState *env, int csrn= o,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *ret_value, >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong new_value, tar= get_ulong write_mask)
> @@ -2054,6 +2125,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_MTVAL]=C2=A0 =C2=A0 =3D { "mtval&q= uot;,=C2=A0 =C2=A0 any,=C2=A0 read_mtval,=C2=A0 =C2=A0 write_mtval=C2=A0 = =C2=A0 },
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_MIP]=C2=A0 =C2=A0 =C2=A0 =3D { "mi= p",=C2=A0 =C2=A0 =C2=A0 any,=C2=A0 NULL,=C2=A0 =C2=A0 NULL, rmw_mip=C2= =A0 =C2=A0 =C2=A0 =C2=A0 },
>=C2=A0 =C2=A0
> +=C2=A0 =C2=A0 /* Execution environment configuration */
> +=C2=A0 =C2=A0 [CSR_MENVCFG]=C2=A0 =3D { "menvcfg",=C2=A0 an= y,=C2=A0 =C2=A0 =C2=A0read_menvcfg,=C2=A0 write_menvcfg, NULL,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 NULL, NULL, PRIV_VERSION_1_12_0},
> +=C2=A0 =C2=A0 [CSR_MENVCFGH] =3D { "menvcfgh", any32,=C2=A0= =C2=A0read_menvcfgh, write_menvcfgh, NULL,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 NULL, NULL, PRIV_VERSION_1_12_0},
> +=C2=A0 =C2=A0 [CSR_SENVCFG]=C2=A0 =3D { "senvcfg",=C2=A0 sm= ode,=C2=A0 =C2=A0read_senvcfg,=C2=A0 write_senvcfg, NULL,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 NULL, NULL, PRIV_VERSION_1_12_0},
> +=C2=A0 =C2=A0 [CSR_HENVCFG]=C2=A0 =3D { "henvcfg",=C2=A0 hm= ode,=C2=A0 =C2=A0read_henvcfg, write_henvcfg, NULL,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 NULL, NULL, PRIV_VERSION_1_12_0},
> +=C2=A0 =C2=A0 [CSR_HENVCFGH] =3D { "henvcfgh", hmode32, rea= d_henvcfgh, write_henvcfgh, NULL,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 NULL, NULL, PRIV_VERSION_1_12_0},
> +
> +
Two new lines here.

Fixed it. Thanks.
=C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Supervisor Trap Setup */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_SSTATUS]=C2=A0 =C2=A0 =3D { "sstat= us",=C2=A0 =C2=A0 smode, read_sstatus,=C2=A0 =C2=A0 write_sstatus, NUL= L,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0read_sstatus_i128=C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0},
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 13b9ab375b95..59479a999b87 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -185,6 +185,31 @@ static const VMStateDescription vmstate_rv128 =3D= {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0};
>=C2=A0 =C2=A0
> +/* TODO: henvcfg need both hyper_needed & envcfg_needed */
> +static bool envcfg_needed(void *opaque)
> +{
> +=C2=A0 =C2=A0 RISCVCPU *cpu =3D opaque;
> +=C2=A0 =C2=A0 CPURISCVState *env =3D &cpu->env;
> +
> +=C2=A0 =C2=A0 return (env->priv_ver >=3D PRIV_VERSION_1_12_0 ? = 1 : 0);
> +}
> +
> +static const VMStateDescription vmstate_envcfg =3D {
> +=C2=A0 =C2=A0 .name =3D "cpu/envcfg",
> +=C2=A0 =C2=A0 .version_id =3D 1,
> +=C2=A0 =C2=A0 .minimum_version_id =3D 1,
> +=C2=A0 =C2=A0 .needed =3D envcfg_needed,
> +=C2=A0 =C2=A0 .fields =3D (VMStateField[]) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINTTL(env.menvcfg, RISCVCPU), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINTTL(env.menvcfgh, RISCVCPU), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINTTL(env.senvcfg, RISCVCPU), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINTTL(env.henvcfg, RISCVCPU), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINTTL(env.henvcfgh, RISCVCPU), > +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_END_OF_LIST()
> +=C2=A0 =C2=A0 }
> +};
> +
>=C2=A0 =C2=A0const VMStateDescription vmstate_riscv_cpu =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0.name =3D "cpu",
>=C2=A0 =C2=A0 =C2=A0 =C2=A0.version_id =3D 3,
> @@ -240,6 +265,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&vmstate_vector,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&vmstate_pointermasking, >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&vmstate_rv128,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 &vmstate_envcfg,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0NULL
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0};

Regards,

Weiwei Li




--
Regards,
Atish
<= /div>
--0000000000003ae62705d6ae7aec-- From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1nDcYD-0008Dd-Oz for mharc-qemu-riscv@gnu.org; Fri, 28 Jan 2022 20:29:13 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54996) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nDcYB-0008DK-Tp for qemu-riscv@nongnu.org; Fri, 28 Jan 2022 20:29:12 -0500 Received: from [2607:f8b0:4864:20::b34] (port=37672 helo=mail-yb1-xb34.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nDcY9-0008Hq-8d for qemu-riscv@nongnu.org; Fri, 28 Jan 2022 20:29:11 -0500 Received: by mail-yb1-xb34.google.com with SMTP id k31so23635054ybj.4 for ; Fri, 28 Jan 2022 17:29:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=atishpatra.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=IL5pbln/bek8VJCd0wjFySOKXrPORR7jhmY7pl3GdRI=; b=oG2O3uRUykU14n31LkSbos/tEYkL0jqLHH9bELocTHhUe42XtBRtE5nzfTcN7W/4nY tvliSPL/n82DMzhW4SKMao4UcXJErqFcQ8JQbsqAc46PUW+94o84LfypMuW0K8/0Wy+e InAAGgPM05ylZoaRmL+5Yilii1GmjMZYuC+4Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=IL5pbln/bek8VJCd0wjFySOKXrPORR7jhmY7pl3GdRI=; b=vVXZuNUzrsHb70Zw67y8d2SLlBMCyYSKDqN7TFMqqeBEBgg2IsWX/faesgfDLA0NaC u7334FitGDTZyw66h/ynhDOFxhxOemY6KJBohGXfsuJTfCsLxCm5xa+5wxdiYQDKachx fbZQBLTDYk5QazImBPHoZqI9vIsuP9Kim+jZ+7TKFbmcpbqUilW036FIGiGyym04I/Z1 6hjQpm6M4Sldw/PPqeT036TSarcBpCLJXXMx/RYdTbbbT8JjZFmR/eOq4BTQwGctAdEo Oj7emEM1/2Af0VeyhonU4MvIo2YgIg5FfzJbOlDEjlwCnTuIVWKzr663tPVL+hea45iG tilw== X-Gm-Message-State: AOAM531u+RR19Xh8yjA14oeOcmEZUPJj5w1jFgYf6cyaKiuHcz3dBEYt 1UgYRb6hzBJgqTvvQHVYawqsXly7H8xSByXkf9tF X-Google-Smtp-Source: ABdhPJzVhnXnjqELzLuM3cAv4lfLBxskTDNnwSNCJPSvMZGS/nowCPpkO49dbmcYrD0mhMvIAfMA+9Q266F3goflnHk= X-Received: by 2002:a25:c344:: with SMTP id t65mr15609219ybf.10.1643419746880; Fri, 28 Jan 2022 17:29:06 -0800 (PST) MIME-Version: 1.0 References: <20220120200735.2739543-1-atishp@rivosinc.com> <20220120200735.2739543-5-atishp@rivosinc.com> <91dbc7a1-f23f-709b-82e8-10e4c96e4482@iscas.ac.cn> In-Reply-To: <91dbc7a1-f23f-709b-82e8-10e4c96e4482@iscas.ac.cn> From: Atish Patra Date: Fri, 28 Jan 2022 17:28:56 -0800 Message-ID: Subject: Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support To: Weiwei Li Cc: Atish Patra , "qemu-devel@nongnu.org Developers" , Anup Patel , Alistair Francis , Bin Meng , "open list:RISC-V" , Palmer Dabbelt Content-Type: multipart/alternative; boundary="0000000000003ae62705d6ae7aec" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::b34 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::b34; envelope-from=atishp@atishpatra.org; helo=mail-yb1-xb34.google.com X-Spam_score_int: 6 X-Spam_score: 0.6 X-Spam_bar: / X-Spam_report: (0.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 29 Jan 2022 01:29:12 -0000 --0000000000003ae62705d6ae7aec Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Jan 26, 2022 at 12:37 AM Weiwei Li wrote: > > =E5=9C=A8 2022/1/21 =E4=B8=8A=E5=8D=884:07, Atish Patra =E5=86=99=E9=81= =93: > > The RISC-V privileged specification v1.12 defines few execution > > environment configuration CSRs that can be used enable/disable > > extensions per privilege levels. > > > > Add the basic support for these CSRs. > > > > Signed-off-by: Atish Patra > > --- > > target/riscv/cpu.h | 8 ++++ > > target/riscv/cpu_bits.h | 31 +++++++++++++++ > > target/riscv/csr.c | 84 ++++++++++++++++++++++++++++++++++++++++= + > > target/riscv/machine.c | 26 +++++++++++++ > > 4 files changed, 149 insertions(+) > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 7f87917204c5..b9462300a472 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -264,6 +264,14 @@ struct CPURISCVState { > > target_ulong spmbase; > > target_ulong upmmask; > > target_ulong upmbase; > > + > > + /* CSRs for execution enviornment configuration */ > > + > > + target_ulong menvcfg; > > + target_ulong menvcfgh; > > I think we needn't maintain seperate menvcfg and menvcfgh, just use > "uint64_t menvcfg" as the way of mstatus. > > unlike mstatush, menvcfgh/henvcfgh will be accessed directly to do runtime predicate for stimecmp/vstimecmp. We have to do the 32 bit shifting during every check which makes the code hard to read at the cost of 2 ulongs. IMO, having separate variables is much simpler. Similar to henvcfg and henvcfg. > > > + target_ulong senvcfg; > > + target_ulong henvcfg; > > + target_ulong henvcfgh; > > #endif > > > > float_status fp_status; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > index f6f90b5cbd52..afb237c2313b 100644 > > --- a/target/riscv/cpu_bits.h > > +++ b/target/riscv/cpu_bits.h > > @@ -177,6 +177,9 @@ > > #define CSR_STVEC 0x105 > > #define CSR_SCOUNTEREN 0x106 > > > > +/* Supervisor Configuration CSRs */ > > +#define CSR_SENVCFG 0x10A > > + > > /* Supervisor Trap Handling */ > > #define CSR_SSCRATCH 0x140 > > #define CSR_SEPC 0x141 > > @@ -204,6 +207,10 @@ > > #define CSR_HTIMEDELTA 0x605 > > #define CSR_HTIMEDELTAH 0x615 > > > > +/* Hypervisor Configuration CSRs */ > > +#define CSR_HENVCFG 0x60A > > +#define CSR_HENVCFGH 0x61A > > + > > /* Virtual CSRs */ > > #define CSR_VSSTATUS 0x200 > > #define CSR_VSIE 0x204 > > @@ -218,6 +225,10 @@ > > #define CSR_MTINST 0x34a > > #define CSR_MTVAL2 0x34b > > > > +/* Machine Configuration CSRs */ > > +#define CSR_MENVCFG 0x30A > > +#define CSR_MENVCFGH 0x31A > > + > > /* Enhanced Physical Memory Protection (ePMP) */ > > #define CSR_MSECCFG 0x747 > > #define CSR_MSECCFGH 0x757 > > @@ -578,6 +589,26 @@ typedef enum RISCVException { > > #define PM_EXT_CLEAN 0x00000002ULL > > #define PM_EXT_DIRTY 0x00000003ULL > > > > +/* Execution enviornment configuration bits */ > > +#define MENVCFG_FIOM (1 << 0) > > +#define MENVCFG_CBE 0x30000ULL > > +#define MENVCFG_CBCFE (1 << 6) > > +#define MENVCFG_CBZE (1 << 7) > > +#define MENVCFG_PBMTE (1 << 62) > > +#define MENVCFG_STCE (1 << 63) > > + > > +#define SENVCFG_FIOM MENVCFG_FIOM > > +#define SENVCFG_CBE MENVCFG_CBE > > +#define SENVCFG_CBCFE MENVCFG_CBCFE > > +#define SENVCFG_CBZE MENVCFG_CBZE > > + > > +#define HENVCFG_FIOM MENVCFG_FIOM > > +#define HENVCFG_CBE MENVCFG_CBE > > +#define HENVCFG_CBCFE MENVCFG_CBCFE > > +#define HENVCFG_CBZE MENVCFG_CBZE > > +#define HENVCFG_PBMTE MENVCFG_PBMTE > > +#define HENVCFG_STCE MENVCFG_STCE > > + > > /* Offsets for every pair of control bits per each priv level */ > > #define XS_OFFSET 0ULL > > #define U_OFFSET 2ULL > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index e66bf2201857..a4bbae7a1bbd 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -853,6 +853,77 @@ static RISCVException write_mtval(CPURISCVState > *env, int csrno, > > return RISCV_EXCP_NONE; > > } > > > > +/* Execution environment configuration setup */ > > +static RISCVException read_menvcfg(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val =3D env->menvcfg; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_menvcfg(CPURISCVState *env, int csrno, > > + target_ulong val) > > +{ > > + env->menvcfg =3D val; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val =3D env->menvcfgh; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, > > + target_ulong val) > > +{ > > + env->menvcfgh =3D val; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException read_senvcfg(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val =3D env->senvcfg; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_senvcfg(CPURISCVState *env, int csrno, > > + target_ulong val) > > +{ > > + env->senvcfg =3D val; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException read_henvcfg(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val =3D env->henvcfg; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, > > + target_ulong val) > > +{ > > + env->henvcfg =3D val; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val =3D env->henvcfgh; > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, > > + target_ulong val) > > +{ > > + env->henvcfgh =3D val; > > + return RISCV_EXCP_NONE; > > +} > > + > > static RISCVException rmw_mip(CPURISCVState *env, int csrno, > > target_ulong *ret_value, > > target_ulong new_value, target_ulong > write_mask) > > @@ -2054,6 +2125,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D= { > > [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval > }, > > [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip > }, > > > > + /* Execution environment configuration */ > > + [CSR_MENVCFG] =3D { "menvcfg", any, read_menvcfg, > write_menvcfg, NULL, > > + NULL, NULL, > PRIV_VERSION_1_12_0}, > > + [CSR_MENVCFGH] =3D { "menvcfgh", any32, read_menvcfgh, > write_menvcfgh, NULL, > > + NULL, NULL, > PRIV_VERSION_1_12_0}, > > + [CSR_SENVCFG] =3D { "senvcfg", smode, read_senvcfg, > write_senvcfg, NULL, > > + NULL, NULL, > PRIV_VERSION_1_12_0}, > > + [CSR_HENVCFG] =3D { "henvcfg", hmode, read_henvcfg, > write_henvcfg, NULL, > > + NULL, NULL, > PRIV_VERSION_1_12_0}, > > + [CSR_HENVCFGH] =3D { "henvcfgh", hmode32, read_henvcfgh, > write_henvcfgh, NULL, > > + NULL, NULL, > PRIV_VERSION_1_12_0}, > > + > > + > Two new lines here. > Fixed it. Thanks. > > /* Supervisor Trap Setup */ > > [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, > write_sstatus, NULL, > > read_sstatus_i128 > }, > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > > index 13b9ab375b95..59479a999b87 100644 > > --- a/target/riscv/machine.c > > +++ b/target/riscv/machine.c > > @@ -185,6 +185,31 @@ static const VMStateDescription vmstate_rv128 =3D = { > > } > > }; > > > > +/* TODO: henvcfg need both hyper_needed & envcfg_needed */ > > +static bool envcfg_needed(void *opaque) > > +{ > > + RISCVCPU *cpu =3D opaque; > > + CPURISCVState *env =3D &cpu->env; > > + > > + return (env->priv_ver >=3D PRIV_VERSION_1_12_0 ? 1 : 0); > > +} > > + > > +static const VMStateDescription vmstate_envcfg =3D { > > + .name =3D "cpu/envcfg", > > + .version_id =3D 1, > > + .minimum_version_id =3D 1, > > + .needed =3D envcfg_needed, > > + .fields =3D (VMStateField[]) { > > + VMSTATE_UINTTL(env.menvcfg, RISCVCPU), > > + VMSTATE_UINTTL(env.menvcfgh, RISCVCPU), > > + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), > > + VMSTATE_UINTTL(env.henvcfg, RISCVCPU), > > + VMSTATE_UINTTL(env.henvcfgh, RISCVCPU), > > + > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > const VMStateDescription vmstate_riscv_cpu =3D { > > .name =3D "cpu", > > .version_id =3D 3, > > @@ -240,6 +265,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { > > &vmstate_vector, > > &vmstate_pointermasking, > > &vmstate_rv128, > > + &vmstate_envcfg, > > NULL > > } > > }; > > Regards, > > Weiwei Li > > > --=20 Regards, Atish --0000000000003ae62705d6ae7aec Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Wed, Jan 26, 2022 at 12:37 AM Weiw= ei Li <liweiwei@iscas.ac.cn&= gt; wrote:

=E5=9C=A8 2022/1/21 =E4=B8=8A=E5=8D=884:07, Atish Patra =E5=86=99=E9=81=93:=
> The RISC-V privileged specification v1.12 defines few execution
> environment configuration CSRs that can be used enable/disable
> extensions per privilege levels.
>
> Add the basic support for these CSRs.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>=C2=A0 =C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 8 ++++
>=C2=A0 =C2=A0target/riscv/cpu_bits.h | 31 +++++++++++++++
>=C2=A0 =C2=A0target/riscv/csr.c=C2=A0 =C2=A0 =C2=A0 | 84 ++++++++++++++= +++++++++++++++++++++++++++
>=C2=A0 =C2=A0target/riscv/machine.c=C2=A0 | 26 +++++++++++++
>=C2=A0 =C2=A04 files changed, 149 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7f87917204c5..b9462300a472 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -264,6 +264,14 @@ struct CPURISCVState {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong spmbase;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong upmmask;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong upmbase;
> +
> +=C2=A0 =C2=A0 /* CSRs for execution enviornment configuration */
> +
> +=C2=A0 =C2=A0 target_ulong menvcfg;
> +=C2=A0 =C2=A0 target_ulong menvcfgh;

I think we needn't maintain seperate menvcfg and menvcfgh, just use "uint64_t menvcfg" as the way of mstatus.


unlike mstatush, menvcfgh/henvcfgh=C2= =A0will be accessed directly to do runtime
predicate for stimecmp= /vstimecmp.
=C2=A0
We have to do the 32 bit shifting during ev= ery check which makes the code hard to read
at the cost of 2 ulon= gs.

IMO, having separate=C2=A0variables is much simpler.

Similar to=C2=A0 henvcfg and henvcfg.

> +=C2=A0 =C2=A0 target_ulong senvcfg;
> +=C2=A0 =C2=A0 target_ulong henvcfg;
> +=C2=A0 =C2=A0 target_ulong henvcfgh;
>=C2=A0 =C2=A0#endif
>=C2=A0 =C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0float_status fp_status;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index f6f90b5cbd52..afb237c2313b 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -177,6 +177,9 @@
>=C2=A0 =C2=A0#define CSR_STVEC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= 0x105
>=C2=A0 =C2=A0#define CSR_SCOUNTEREN=C2=A0 =C2=A0 =C2=A0 0x106
>=C2=A0 =C2=A0
> +/* Supervisor Configuration CSRs */
> +#define CSR_SENVCFG=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x10A
> +
>=C2=A0 =C2=A0/* Supervisor Trap Handling */
>=C2=A0 =C2=A0#define CSR_SSCRATCH=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x140
>=C2=A0 =C2=A0#define CSR_SEPC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = 0x141
> @@ -204,6 +207,10 @@
>=C2=A0 =C2=A0#define CSR_HTIMEDELTA=C2=A0 =C2=A0 =C2=A0 0x605
>=C2=A0 =C2=A0#define CSR_HTIMEDELTAH=C2=A0 =C2=A0 =C2=A00x615
>=C2=A0 =C2=A0
> +/* Hypervisor Configuration CSRs */
> +#define CSR_HENVCFG=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x60A
> +#define CSR_HENVCFGH=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x61A
> +
>=C2=A0 =C2=A0/* Virtual CSRs */
>=C2=A0 =C2=A0#define CSR_VSSTATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x200
>=C2=A0 =C2=A0#define CSR_VSIE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = 0x204
> @@ -218,6 +225,10 @@
>=C2=A0 =C2=A0#define CSR_MTINST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x34a=
>=C2=A0 =C2=A0#define CSR_MTVAL2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x34b=
>=C2=A0 =C2=A0
> +/* Machine Configuration CSRs */
> +#define CSR_MENVCFG=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x30A
> +#define CSR_MENVCFGH=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x31A
> +
>=C2=A0 =C2=A0/* Enhanced Physical Memory Protection (ePMP) */
>=C2=A0 =C2=A0#define CSR_MSECCFG=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x747=
>=C2=A0 =C2=A0#define CSR_MSECCFGH=C2=A0 =C2=A0 =C2=A0 =C2=A0 0x757
> @@ -578,6 +589,26 @@ typedef enum RISCVException {
>=C2=A0 =C2=A0#define PM_EXT_CLEAN=C2=A0 =C2=A0 0x00000002ULL
>=C2=A0 =C2=A0#define PM_EXT_DIRTY=C2=A0 =C2=A0 0x00000003ULL
>=C2=A0 =C2=A0
> +/* Execution enviornment configuration bits */
> +#define MENVCFG_FIOM=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 0)
> +#define MENVCFG_CBE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x30000ULL
> +#define MENVCFG_CBCFE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 6)
> +#define MENVCFG_CBZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 7)
> +#define MENVCFG_PBMTE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 62)
> +#define MENVCFG_STCE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 63)
> +
> +#define SENVCFG_FIOM=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_FIOM
> +#define SENVCFG_CBE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBE
> +#define SENVCFG_CBCFE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBCFE
> +#define SENVCFG_CBZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_CBZE
> +
> +#define HENVCFG_FIOM=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_FIOM
> +#define HENVCFG_CBE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBE
> +#define HENVCFG_CBCFE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_CBCFE
> +#define HENVCFG_CBZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_CBZE
> +#define HENVCFG_PBMTE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 MENVCFG_PBMTE
> +#define HENVCFG_STCE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MENVCFG_STCE
> +
>=C2=A0 =C2=A0/* Offsets for every pair of control bits per each priv le= vel */
>=C2=A0 =C2=A0#define XS_OFFSET=C2=A0 =C2=A0 0ULL
>=C2=A0 =C2=A0#define U_OFFSET=C2=A0 =C2=A0 =C2=A02ULL
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index e66bf2201857..a4bbae7a1bbd 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -853,6 +853,77 @@ static RISCVException write_mtval(CPURISCVState *= env, int csrno,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0return RISCV_EXCP_NONE;
>=C2=A0 =C2=A0}
>=C2=A0 =C2=A0
> +/* Execution environment configuration setup */
> +static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *val)
> +{
> +=C2=A0 =C2=A0 *val =3D env->menvcfg;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_menvcfg(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong val)
> +{
> +=C2=A0 =C2=A0 env->menvcfg =3D val;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *val)
> +{
> +=C2=A0 =C2=A0 *val =3D env->menvcfgh;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong val)
> +{
> +=C2=A0 =C2=A0 env->menvcfgh =3D val;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *val)
> +{
> +=C2=A0 =C2=A0 *val =3D env->senvcfg;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_senvcfg(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong val)
> +{
> +=C2=A0 =C2=A0 env->senvcfg =3D val;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *val)
> +{
> +=C2=A0 =C2=A0 *val =3D env->henvcfg;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong val)
> +{
> +=C2=A0 =C2=A0 env->henvcfg =3D val;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *val)
> +{
> +=C2=A0 =C2=A0 *val =3D env->henvcfgh;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 target_ulong val)
> +{
> +=C2=A0 =C2=A0 env->henvcfgh =3D val;
> +=C2=A0 =C2=A0 return RISCV_EXCP_NONE;
> +}
> +
>=C2=A0 =C2=A0static RISCVException rmw_mip(CPURISCVState *env, int csrn= o,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *ret_value, >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong new_value, tar= get_ulong write_mask)
> @@ -2054,6 +2125,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_MTVAL]=C2=A0 =C2=A0 =3D { "mtval&q= uot;,=C2=A0 =C2=A0 any,=C2=A0 read_mtval,=C2=A0 =C2=A0 write_mtval=C2=A0 = =C2=A0 },
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_MIP]=C2=A0 =C2=A0 =C2=A0 =3D { "mi= p",=C2=A0 =C2=A0 =C2=A0 any,=C2=A0 NULL,=C2=A0 =C2=A0 NULL, rmw_mip=C2= =A0 =C2=A0 =C2=A0 =C2=A0 },
>=C2=A0 =C2=A0
> +=C2=A0 =C2=A0 /* Execution environment configuration */
> +=C2=A0 =C2=A0 [CSR_MENVCFG]=C2=A0 =3D { "menvcfg",=C2=A0 an= y,=C2=A0 =C2=A0 =C2=A0read_menvcfg,=C2=A0 write_menvcfg, NULL,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 NULL, NULL, PRIV_VERSION_1_12_0},
> +=C2=A0 =C2=A0 [CSR_MENVCFGH] =3D { "menvcfgh", any32,=C2=A0= =C2=A0read_menvcfgh, write_menvcfgh, NULL,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 NULL, NULL, PRIV_VERSION_1_12_0},
> +=C2=A0 =C2=A0 [CSR_SENVCFG]=C2=A0 =3D { "senvcfg",=C2=A0 sm= ode,=C2=A0 =C2=A0read_senvcfg,=C2=A0 write_senvcfg, NULL,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 NULL, NULL, PRIV_VERSION_1_12_0},
> +=C2=A0 =C2=A0 [CSR_HENVCFG]=C2=A0 =3D { "henvcfg",=C2=A0 hm= ode,=C2=A0 =C2=A0read_henvcfg, write_henvcfg, NULL,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 NULL, NULL, PRIV_VERSION_1_12_0},
> +=C2=A0 =C2=A0 [CSR_HENVCFGH] =3D { "henvcfgh", hmode32, rea= d_henvcfgh, write_henvcfgh, NULL,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 NULL, NULL, PRIV_VERSION_1_12_0},
> +
> +
Two new lines here.

Fixed it. Thanks.
=C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Supervisor Trap Setup */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0[CSR_SSTATUS]=C2=A0 =C2=A0 =3D { "sstat= us",=C2=A0 =C2=A0 smode, read_sstatus,=C2=A0 =C2=A0 write_sstatus, NUL= L,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0read_sstatus_i128=C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0},
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 13b9ab375b95..59479a999b87 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -185,6 +185,31 @@ static const VMStateDescription vmstate_rv128 =3D= {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0};
>=C2=A0 =C2=A0
> +/* TODO: henvcfg need both hyper_needed & envcfg_needed */
> +static bool envcfg_needed(void *opaque)
> +{
> +=C2=A0 =C2=A0 RISCVCPU *cpu =3D opaque;
> +=C2=A0 =C2=A0 CPURISCVState *env =3D &cpu->env;
> +
> +=C2=A0 =C2=A0 return (env->priv_ver >=3D PRIV_VERSION_1_12_0 ? = 1 : 0);
> +}
> +
> +static const VMStateDescription vmstate_envcfg =3D {
> +=C2=A0 =C2=A0 .name =3D "cpu/envcfg",
> +=C2=A0 =C2=A0 .version_id =3D 1,
> +=C2=A0 =C2=A0 .minimum_version_id =3D 1,
> +=C2=A0 =C2=A0 .needed =3D envcfg_needed,
> +=C2=A0 =C2=A0 .fields =3D (VMStateField[]) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINTTL(env.menvcfg, RISCVCPU), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINTTL(env.menvcfgh, RISCVCPU), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINTTL(env.senvcfg, RISCVCPU), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINTTL(env.henvcfg, RISCVCPU), > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_UINTTL(env.henvcfgh, RISCVCPU), > +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_END_OF_LIST()
> +=C2=A0 =C2=A0 }
> +};
> +
>=C2=A0 =C2=A0const VMStateDescription vmstate_riscv_cpu =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0.name =3D "cpu",
>=C2=A0 =C2=A0 =C2=A0 =C2=A0.version_id =3D 3,
> @@ -240,6 +265,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&vmstate_vector,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&vmstate_pointermasking, >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&vmstate_rv128,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 &vmstate_envcfg,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0NULL
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0};

Regards,

Weiwei Li




--
Regards,
Atish
<= /div>
--0000000000003ae62705d6ae7aec--