Re: CAN question: how to trace frame errors?

[Holger Schurig <holgerschurig@gmail.com>]

> and while the CPU supports different interrupt priorities, the 3.4 TZIC code
> simply doesn't provide the functions to change it.

I don't know the i.MX5x and it's TZIC, only the i.MX6 ... and only a
bit. But I think there it's not a limitation in the silicon, but in
the software (Linux in our case, e.g. drivers/irqchips/gic*). The
i.MX6 uses the GIC (described in the ARM MPCORE reference manual). And
there it says:

------------------------
The interrupt distributor centralizes all interrupt sources before
dispatching them to each individual Cortex-A9 processor. The Interrupt
Distributor arbitrates in the following priority order:
1. Highest priority interrupts. These have the lowest value in the
Interrupt Priority Register (ICDIPTR)
2. For interrupts with the same priority value, the Interrupt
Distributor arbitrates on the interrupt ID number. It dispatches the
smaller ID number first
3. For aliased SGI with the same priority value and the same ID
number, the Interrupt Distributor arbitrates on the source CPU number.
It dispatches the smaller CPU number first.
------------------------

This register ICDIPTR is called GIC_DIST_PRI in Linux and they all get
set to a fixed value. So it's the IRQ number that set's the IRQ
priority in current Linux.


And btw, thanks for your patch. I'll probably rewrite it to use kfifo,
which is a ringbuffer already contained in Linux (see
include/linux/kfifo.h), I think that will increase it's chance of
inclusion.