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Tsirkin" X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=205.139.110.61; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/01 02:02:06 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Prasad J Pandit , QEMU Developers , Alexander Bulekov , Anatoly Trosinenko , Ren Ding , Hanqing Zhao Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Jun 1, 2020 at 8:02 AM Philippe Mathieu-Daud=C3=A9 wrote: > On 6/1/20 7:14 AM, P J P wrote: > > From: Prasad J Pandit > > > > While doing msi-x mmio operations, a guest may send an address > > that leads to an OOB access issue. Add valid.accepts methods to > > ensure that ensuing mmio r/w operation don't go beyond regions. > > > > Fixes: CVE-2020-xxxxx Oh and please also add: Cc: qemu-stable@nongnu.org > > > Reported-by: Ren Ding > > Reported-by: Hanqing Zhao > > Reported-by: Anatoly Trosinenko > > Reported-by: Alexander Bulekov > > Signed-off-by: Prasad J Pandit > > --- > > hw/pci/msix.c | 20 ++++++++++++++++++++ > > 1 file changed, 20 insertions(+) > > > > diff --git a/hw/pci/msix.c b/hw/pci/msix.c > > index 29187898f2..d90d66a3b8 100644 > > --- a/hw/pci/msix.c > > +++ b/hw/pci/msix.c > > @@ -193,6 +193,15 @@ static void msix_table_mmio_write(void *opaque, hw= addr addr, > > msix_handle_mask_update(dev, vector, was_masked); > > } > > > > +static bool msix_table_accepts(void *opaque, hwaddr addr, unsigned siz= e, > > + bool is_write, MemTxAttrs attrs) > > +{ > > + PCIDevice *dev =3D opaque; > > + uint16_t tbl_size =3D dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE; > > + > > + return dev->msix_table + addr + 4 <=3D dev->msix_table + tbl_size; > > Can be simplified as: > > return addr + 4 <=3D dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE; > > > +} > > + > > static const MemoryRegionOps msix_table_mmio_ops =3D { > > .read =3D msix_table_mmio_read, > > .write =3D msix_table_mmio_write, > > @@ -200,6 +209,7 @@ static const MemoryRegionOps msix_table_mmio_ops = =3D { > > .valid =3D { > > .min_access_size =3D 4, > > .max_access_size =3D 4, > > + .accepts =3D msix_table_accepts > > }, > > }; > > > > @@ -221,6 +231,15 @@ static void msix_pba_mmio_write(void *opaque, hwad= dr addr, > > { > > } > > > > +static bool msix_pba_accepts(void *opaque, hwaddr addr, unsigned size, > > + bool is_write, MemTxAttrs attrs) > > +{ > > + PCIDevice *dev =3D opaque; > > + uint16_t pba_size =3D QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8; > > + > > + return dev->msix_pba + addr + 4 <=3D dev->msix_pba + pba_size; > > Can be simplified as: > > return addr + 4 <=3D QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8; > > > +} > > + > > static const MemoryRegionOps msix_pba_mmio_ops =3D { > > .read =3D msix_pba_mmio_read, > > .write =3D msix_pba_mmio_write, > > @@ -228,6 +247,7 @@ static const MemoryRegionOps msix_pba_mmio_ops =3D = { > > .valid =3D { > > .min_access_size =3D 4, > > .max_access_size =3D 4, > > + .accepts =3D msix_pba_accepts > > }, > > }; > > > > >