From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
To: Shashank Sharma <shashank.sharma@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>,
arvind.yadav@amd.com, Christian Koenig <christian.koenig@amd.com>,
amd-gfx@lists.freedesktop.org, arunpravin.paneerselvam@amd.com
Subject: Re: [RFC 1/7] drm/amdgpu: UAPI for user queue management
Date: Sat, 24 Dec 2022 21:20:59 +0100 [thread overview]
Message-ID: <CAP+8YyGPy5oXpOcuWfaS1vNhGajG1VGZc4p_QiUxaLAFCtt5KQ@mail.gmail.com> (raw)
In-Reply-To: <20221223193655.1972-2-shashank.sharma@amd.com>
On Fri, Dec 23, 2022 at 8:37 PM Shashank Sharma <shashank.sharma@amd.com> wrote:
>
> From: Alex Deucher <alexander.deucher@amd.com>
>
> This patch intorduces new UAPI/IOCTL for usermode graphics
> queue. The userspace app will fill this structure and request
> the graphics driver to add a graphics work queue for it. The
> output of this UAPI is a queue id.
>
> This UAPI maps the queue into GPU, so the graphics app can start
> submitting work to the queue as soon as the call returns.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian Koenig <christian.koenig@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
> ---
> include/uapi/drm/amdgpu_drm.h | 52 +++++++++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 0d93ec132ebb..a3d0dd6f62c5 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -54,6 +54,7 @@ extern "C" {
> #define DRM_AMDGPU_VM 0x13
> #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
> #define DRM_AMDGPU_SCHED 0x15
> +#define DRM_AMDGPU_USERQ 0x16
>
> #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
> #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
> @@ -71,6 +72,7 @@ extern "C" {
> #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
> #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
> #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
> +#define DRM_IOCTL_AMDGPU_USERQ DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
>
> /**
> * DOC: memory domains
> @@ -288,6 +290,56 @@ union drm_amdgpu_ctx {
> union drm_amdgpu_ctx_out out;
> };
>
> +/* user queue IOCTL */
> +#define AMDGPU_USERQ_OP_CREATE 1
> +#define AMDGPU_USERQ_OP_FREE 2
> +
> +#define AMDGPU_USERQ_MQD_FLAGS_SECURE (1 << 0)
> +#define AMDGPU_USERQ_MQD_FLAGS_AQL (1 << 1)
Can we document what AQL means here?
> +
> +struct drm_amdgpu_userq_mqd {
> + /** Flags: AMDGPU_USERQ_MQD_FLAGS_* */
> + __u32 flags;
> + /** IP type: AMDGPU_HW_IP_* */
> + __u32 ip_type;
> + /** GEM object handle */
> + __u32 doorbell_handle;
> + /** Doorbell offset in dwords */
> + __u32 doorbell_offset;
What are the doorbell handle/offset for? I don't see any of them used
in the rest of the series (we only check the handle isn't 0, which
isn't enough validation for a GEM handle to consider it valid), and
the kernel seems to allocate some kind of doorbell index in patch 4.
Does userspace need to know about that one? (similarly use_doorbell in
that patch seems like it is never explicitly written to)
The other questions I have are about how this interacts with memory
management. Does this have access to all BOs allocated with
AMDGPU_GEM_CREATE_VM_ALWAYS_VALID? What about imported BOs? How does
this interact with VA unmap/map operations? (AFAICT we have no way to
tell if pagetable modifying operations are complete from userspace for
now). What happens if we need to spill BOs from VRAM due to
(cross-process) memory pressure?
> + /** GPU virtual address of the queue */
> + __u64 queue_va;
> + /** Size of the queue in bytes */
> + __u64 queue_size;
> + /** GPU virtual address of the rptr */
> + __u64 rptr_va;
> + /** GPU virtual address of the wptr */
> + __u64 wptr_va;
> +};
> +
> +struct drm_amdgpu_userq_in {
> + /** AMDGPU_USERQ_OP_* */
> + __u32 op;
> + /** Flags */
> + __u32 flags;
> + /** Context handle to associate the queue with */
> + __u32 ctx_id;
> + __u32 pad;
> + /** Queue descriptor */
> + struct drm_amdgpu_userq_mqd mqd;
> +};
> +
> +struct drm_amdgpu_userq_out {
> + /** Queue handle */
> + __u32 q_id;
> + /** Flags */
> + __u32 flags;
> +};
> +
> +union drm_amdgpu_userq {
> + struct drm_amdgpu_userq_in in;
> + struct drm_amdgpu_userq_out out;
> +};
> +
> /* vm ioctl */
> #define AMDGPU_VM_OP_RESERVE_VMID 1
> #define AMDGPU_VM_OP_UNRESERVE_VMID 2
> --
> 2.34.1
>
next prev parent reply other threads:[~2022-12-24 20:21 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-23 19:36 [RFC 0/7] RFC: Usermode queue for AMDGPU driver Shashank Sharma
2022-12-23 19:36 ` [RFC 1/7] drm/amdgpu: UAPI for user queue management Shashank Sharma
2022-12-24 20:20 ` Bas Nieuwenhuizen [this message]
2022-12-27 16:58 ` Alex Deucher
2023-01-02 11:27 ` Christian König
2023-01-03 19:51 ` Alex Deucher
2023-01-02 13:26 ` Christian König
2023-01-03 14:23 ` Alex Deucher
2023-01-03 18:29 ` Felix Kuehling
2023-01-03 19:17 ` Liu, Shaoyun
2023-01-03 19:22 ` Alex Deucher
2023-01-03 19:25 ` Liu, Shaoyun
2023-01-03 19:52 ` Alex Deucher
2023-01-03 20:05 ` Felix Kuehling
2023-01-03 19:18 ` Alex Deucher
2022-12-23 19:36 ` [RFC 2/7] drm/amdgpu: Add usermode queue for gfx work Shashank Sharma
2022-12-24 18:19 ` Oded Gabbay
2022-12-26 10:34 ` Shashank Sharma
2022-12-25 15:44 ` Christian König
2022-12-26 10:41 ` Shashank Sharma
2023-01-02 12:39 ` Christian König
2023-01-03 9:12 ` Shashank Sharma
2023-01-03 9:15 ` Christian König
2023-01-03 9:22 ` Shashank Sharma
2023-01-03 9:35 ` Christian König
2023-01-03 14:34 ` Alex Deucher
2023-01-03 14:50 ` Christian König
2022-12-29 17:41 ` Alex Deucher
2023-01-02 13:53 ` Christian König
2023-01-03 9:32 ` Shashank Sharma
2023-01-03 9:16 ` Shashank Sharma
2023-01-04 8:55 ` Zhu, Jiadong
2023-01-04 8:58 ` Shashank Sharma
2022-12-23 19:36 ` [RFC 3/7] drm/amdgpu: Create MQD for userspace queue Shashank Sharma
2022-12-29 17:47 ` Alex Deucher
2023-01-03 9:36 ` Shashank Sharma
2023-01-03 18:37 ` Felix Kuehling
2023-01-04 6:21 ` Yadav, Arvind
2023-01-04 9:10 ` Christian König
2023-01-04 9:13 ` Shashank Sharma
2023-01-04 9:17 ` Christian König
2023-01-04 9:23 ` Shashank Sharma
2023-01-04 14:35 ` Felix Kuehling
2023-01-04 14:38 ` Yadav, Arvind
2023-01-04 14:41 ` Shashank Sharma
2023-01-04 14:28 ` Alex Deucher
2022-12-23 19:36 ` [RFC 4/7] drm/amdgpu: Allocate doorbell slot for user queue Shashank Sharma
2022-12-29 17:50 ` Alex Deucher
2023-01-03 9:37 ` Shashank Sharma
2022-12-23 19:36 ` [RFC 5/7] drm/amdgpu: Create context for usermode queue Shashank Sharma
2022-12-29 17:54 ` Alex Deucher
2023-01-03 9:40 ` Shashank Sharma
2023-01-03 14:48 ` Alex Deucher
2022-12-23 19:36 ` [RFC 6/7] drm/amdgpu: Map userqueue into HW Shashank Sharma
2022-12-29 17:51 ` Alex Deucher
2023-01-03 9:38 ` Shashank Sharma
2022-12-23 19:36 ` [RFC 7/7] drm/amdgpu: Secure semaphore for usermode queue Shashank Sharma
2022-12-25 10:07 ` Zhang, Yifan
2022-12-27 9:32 ` Arunpravin Paneer Selvam
2022-12-29 18:02 ` [RFC 0/7] RFC: Usermode queue for AMDGPU driver Alex Deucher
2023-01-03 9:43 ` Shashank Sharma
2023-01-03 9:47 ` Christian König
2023-01-03 10:00 ` Shashank Sharma
2023-01-03 10:02 ` Christian König
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