From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753147AbdCTICc (ORCPT ); Mon, 20 Mar 2017 04:02:32 -0400 Received: from mail-yw0-f194.google.com ([209.85.161.194]:34220 "EHLO mail-yw0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752784AbdCTIC1 (ORCPT ); Mon, 20 Mar 2017 04:02:27 -0400 MIME-Version: 1.0 In-Reply-To: References: <20170311194702.28754-1-khuey@kylehuey.com> <20170311194702.28754-7-khuey@kylehuey.com> From: Kyle Huey Date: Mon, 20 Mar 2017 01:01:54 -0700 Message-ID: Subject: Re: [PATCH v15 6/9] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID To: Thomas Gleixner Cc: "Robert O'Callahan" , Andy Lutomirski , Ingo Molnar , "H. Peter Anvin" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , Paolo Bonzini , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Jeff Dike , Richard Weinberger , Alexander Viro , Shuah Khan , Dave Hansen , Borislav Petkov , Peter Zijlstra , Boris Ostrovsky , Len Brown , Dmitry Safonov , "Rafael J. Wysocki" , David Matlack , Nadav Amit , Andi Kleen , open list , "open list:USER-MODE LINUX (UML)" , "open list:USER-MODE LINUX (UML)" , "open list:KERNEL SELFTEST FRAMEWORK" , kvm list Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 14, 2017 at 1:36 PM, Thomas Gleixner wrote: > On Sat, 11 Mar 2017, Kyle Huey wrote: >> static void init_intel_misc_features(struct cpuinfo_x86 *c) >> { >> u64 msr; >> >> + if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) >> + return; >> + >> + msr = 0; >> + wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); >> + this_cpu_write(msr_misc_features_shadow, msr); >> + >> if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { >> if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) >> set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); >> } >> >> probe_xeon_phi_r3mwait(c); > > The way you are doing it breaks the ring3 mwait feature because you > overwrite the R3MWAIT bit the first time you update the MSR on context > switch. Indeed. Good catch. - Kyle From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kyle Huey Subject: Re: [PATCH v15 6/9] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Date: Mon, 20 Mar 2017 01:01:54 -0700 Message-ID: References: <20170311194702.28754-1-khuey@kylehuey.com> <20170311194702.28754-7-khuey@kylehuey.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Cc: "Robert O'Callahan" , Andy Lutomirski , Ingo Molnar , "H. Peter Anvin" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , Paolo Bonzini , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Jeff Dike , Richard Weinberger , Alexander Viro , Shuah Khan , Dave Hansen , Borislav Petkov , Peter Zijlstra , Boris Ostrovsky , Len Brown , Dmitry Safonov , "Rafael J. Wysocki" , David Matlack Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On Tue, Mar 14, 2017 at 1:36 PM, Thomas Gleixner wrote: > On Sat, 11 Mar 2017, Kyle Huey wrote: >> static void init_intel_misc_features(struct cpuinfo_x86 *c) >> { >> u64 msr; >> >> + if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) >> + return; >> + >> + msr = 0; >> + wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); >> + this_cpu_write(msr_misc_features_shadow, msr); >> + >> if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { >> if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) >> set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); >> } >> >> probe_xeon_phi_r3mwait(c); > > The way you are doing it breaks the ring3 mwait feature because you > overwrite the R3MWAIT bit the first time you update the MSR on context > switch. Indeed. Good catch. - Kyle