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Mon, 23 May 2022 05:48:45 -0700 (PDT) MIME-Version: 1.0 References: <20220522155046.260146-1-tmaimon77@gmail.com> <20220522155046.260146-9-tmaimon77@gmail.com> <6fa3d94c-294d-1c6c-5738-6d15b2e17e90@linux.intel.com> In-Reply-To: <6fa3d94c-294d-1c6c-5738-6d15b2e17e90@linux.intel.com> From: Tomer Maimon Date: Mon, 23 May 2022 15:48:34 +0300 Message-ID: Subject: Re: [PATCH v1 08/19] clk: npcm8xx: add clock controller To: =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= List-Id: Cc: Avi Fishman , Tali Perry , Joel Stanley , Patrick Venture , Nancy Yuen , Benjamin Fair , Rob Herring , krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, Philipp Zabel , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , catalin.marinas@arm.com, will@kernel.org, Arnd Bergmann , Olof Johansson , Jiri Slaby , shawnguo@kernel.org, bjorn.andersson@linaro.org, geert+renesas@glider.be, marcel.ziswiler@toradex.com, Vinod Koul , biju.das.jz@bp.renesas.com, nobuhiro1.iwamatsu@toshiba.co.jp, robert.hancock@calian.com, =?UTF-8?Q?Jonathan_Neusch=C3=A4fer?= , lkundrak@v3.sk, soc@kernel.org, devicetree , LKML , linux-clk@vger.kernel.org, linux-serial , linux-watchdog@vger.kernel.org, Linux ARM Content-Type: multipart/alternative; boundary="000000000000b6847e05dfad428a" --000000000000b6847e05dfad428a Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Ilpo, Thanks for your comments. the patch will modify according to your comments and will be sent in the next kernel revision 5.19.rc1 On Mon, 23 May 2022 at 10:07, Ilpo J=C3=A4rvinen wrote: > On Sun, 22 May 2022, Tomer Maimon wrote: > > > Nuvoton Arbel BMC NPCM7XX contains an integrated clock controller, whic= h > > generates and supplies clocks to all modules within the BMC. > > > > Signed-off-by: Tomer Maimon > > > +static struct clk_hw * > > +npcm8xx_clk_register_pll(void __iomem *pllcon, const char *name, > > + const char *parent_name, unsigned long flags) > > +{ > > + struct npcm8xx_clk_pll *pll; > > + struct clk_init_data init; > > + struct clk_hw *hw; > > + int ret; > > + > > + pll =3D kzalloc(sizeof(*pll), GFP_KERNEL); > > + if (!pll) > > + return ERR_PTR(-ENOMEM); > > + > > + pr_debug("%s reg, name=3D%s, p=3D%s\n", __func__, name, parent_na= me); > > + > > + init.name =3D name; > > + init.ops =3D &npcm8xx_clk_pll_ops; > > + init.parent_names =3D &parent_name; > > + init.num_parents =3D 1; > > + init.flags =3D flags; > > + > > + pll->pllcon =3D pllcon; > > + pll->hw.init =3D &init; > > + > > + hw =3D &pll->hw; > > + > > + ret =3D clk_hw_register(NULL, hw); > > + if (ret) { > > + kfree(pll); > > + hw =3D ERR_PTR(ret); > > + } > > + > > + return hw; > > +} > > + > > +#define NPCM8XX_CLKEN1 (0x00) > > +#define NPCM8XX_CLKEN2 (0x28) > > +#define NPCM8XX_CLKEN3 (0x30) > > +#define NPCM8XX_CLKEN4 (0x70) > > +#define NPCM8XX_CLKSEL (0x04) > > +#define NPCM8XX_CLKDIV1 (0x08) > > +#define NPCM8XX_CLKDIV2 (0x2C) > > +#define NPCM8XX_CLKDIV3 (0x58) > > +#define NPCM8XX_CLKDIV4 (0x7C) > > +#define NPCM8XX_PLLCON0 (0x0C) > > +#define NPCM8XX_PLLCON1 (0x10) > > +#define NPCM8XX_PLLCON2 (0x54) > > +#define NPCM8XX_SWRSTR (0x14) > > +#define NPCM8XX_IRQWAKECON (0x18) > > +#define NPCM8XX_IRQWAKEFLAG (0x1C) > > +#define NPCM8XX_IPSRST1 (0x20) > > +#define NPCM8XX_IPSRST2 (0x24) > > +#define NPCM8XX_IPSRST3 (0x34) > > +#define NPCM8XX_WD0RCR (0x38) > > +#define NPCM8XX_WD1RCR (0x3C) > > +#define NPCM8XX_WD2RCR (0x40) > > +#define NPCM8XX_SWRSTC1 (0x44) > > +#define NPCM8XX_SWRSTC2 (0x48) > > +#define NPCM8XX_SWRSTC3 (0x4C) > > +#define NPCM8XX_SWRSTC4 (0x50) > > +#define NPCM8XX_CORSTC (0x5C) > > +#define NPCM8XX_PLLCONG (0x60) > > +#define NPCM8XX_AHBCKFI (0x64) > > +#define NPCM8XX_SECCNT (0x68) > > +#define NPCM8XX_CNTR25M (0x6C) > > +#define NPCM8XX_THRTL_CNT (0xC0) > > + > > +struct npcm8xx_clk_gate_data { > > + u32 reg; > > + u8 bit_idx; > > + const char *name; > > + const char *parent_name; > > + unsigned long flags; > > + /* > > + * If this clock is exported via DT, set onecell_idx to constant > > + * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h > for > > + * this specific clock. Otherwise, set to -1. > > + */ > > + int onecell_idx; > > +}; > > + > > +struct npcm8xx_clk_mux_data { > > + u8 shift; > > + u8 mask; > > + u32 *table; > > + const char *name; > > + const char * const *parent_names; > > + u8 num_parents; > > + unsigned long flags; > > + /* > > + * If this clock is exported via DT, set onecell_idx to constant > > + * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h > for > > + * this specific clock. Otherwise, set to -1. > > + */ > > + int onecell_idx; > > + > > +}; > > + > > +struct npcm8xx_clk_div_fixed_data { > > + u8 mult; > > + u8 div; > > + const char *name; > > + const char *parent_name; > > + u8 clk_divider_flags; > > + /* > > + * If this clock is exported via DT, set onecell_idx to constant > > + * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h > for > > + * this specific clock. Otherwise, set to -1. > > + */ > > + int onecell_idx; > > +}; > > + > > +struct npcm8xx_clk_div_data { > > + u32 reg; > > + u8 shift; > > + u8 width; > > + const char *name; > > + const char *parent_name; > > + u8 clk_divider_flags; > > + unsigned long flags; > > + /* > > + * If this clock is exported via DT, set onecell_idx to constant > > + * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h > for > > + * this specific clock. Otherwise, set to -1. > > + */ > > + int onecell_idx; > > +}; > > + > > +struct npcm8xx_clk_pll_data { > > + u32 reg; > > + const char *name; > > + const char *parent_name; > > + unsigned long flags; > > + /* > > + * If this clock is exported via DT, set onecell_idx to constant > > + * defined in include/dt-bindings/clock/nuvoton, NPCM8XX-clock.h > for > > + * this specific clock. Otherwise, set to -1. > > + */ > > + int onecell_idx; > > +}; > > + > > > > +/* > > + * Single copy of strings used to refer to clocks within this driver > indexed by > > + * above enum. > > + */ > > +#define NPCM8XX_CLK_S_REFCLK "refclk" > > +#define NPCM8XX_CLK_S_SYSBYPCK "sysbypck" > > +#define NPCM8XX_CLK_S_MCBYPCK "mcbypck" > > +#define NPCM8XX_CLK_S_GFXBYPCK "gfxbypck" > > +#define NPCM8XX_CLK_S_PLL0 "pll0" > > +#define NPCM8XX_CLK_S_PLL1 "pll1" > > +#define NPCM8XX_CLK_S_PLL1_DIV2 "pll1_div2" > > +#define NPCM8XX_CLK_S_PLL2 "pll2" > > +#define NPCM8XX_CLK_S_PLL_GFX "pll_gfx" > > +#define NPCM8XX_CLK_S_PLL2_DIV2 "pll2_div2" > > +#define NPCM8XX_CLK_S_PIX_MUX "gfx_pixel" > > +#define NPCM8XX_CLK_S_GPRFSEL_MUX "gprfsel_mux" > > +#define NPCM8XX_CLK_S_MC_MUX "mc_phy" > > +#define NPCM8XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/ > > Add spaces around comment. > > > +#define NPCM8XX_CLK_S_MC "mc" > > +#define NPCM8XX_CLK_S_AXI "axi" /*AKA CLK2*/ > > +#define NPCM8XX_CLK_S_AHB "ahb" /*AKA CLK4*/ > > Ditto. > > > +static void __init npcm8xx_clk_init(struct device_node *clk_np) > > +{ > > + struct clk_hw_onecell_data *npcm8xx_clk_data; > > + void __iomem *clk_base; > > + struct resource res; > > + struct clk_hw *hw; > > + int ret; > > + int i; > > + > > + ret =3D of_address_to_resource(clk_np, 0, &res); > > + if (ret) { > > + pr_err("%pOFn: failed to get resource, ret %d\n", clk_np, > ret); > > + return; > > + } > > + > > + clk_base =3D ioremap(res.start, resource_size(&res)); > > + if (!clk_base) > > + goto npcm8xx_init_error; > > + > > + npcm8xx_clk_data =3D kzalloc(struct_size(npcm8xx_clk_data, hws, > > + NPCM8XX_NUM_CLOCKS), > GFP_KERNEL); > > + if (!npcm8xx_clk_data) > > + goto npcm8xx_init_np_err; > > + > > + npcm8xx_clk_data->num =3D NPCM8XX_NUM_CLOCKS; > > + > > + for (i =3D 0; i < NPCM8XX_NUM_CLOCKS; i++) > > + npcm8xx_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); > > + > > + /* Register plls */ > > + for (i =3D 0; i < ARRAY_SIZE(npcm8xx_plls); i++) { > > + const struct npcm8xx_clk_pll_data *pll_data =3D > &npcm8xx_plls[i]; > > + > > + hw =3D npcm8xx_clk_register_pll(clk_base + pll_data->reg, > > + pll_data->name, > > + pll_data->parent_name, > > + pll_data->flags); > > + if (IS_ERR(hw)) { > > Who deregisters the already registered plls on error paths? > > You might want to consider devm_ variants in npcm8xx_clk_register_pll() t= o > make the cleanup simpler. > > Please check the other error path rollbacks from this point onward too. > > + pr_err("npcm8xx_clk: Can't register pll\n"); > > + goto npcm8xx_init_fail; > > + } > > + > > + if (pll_data->onecell_idx >=3D 0) > > + npcm8xx_clk_data->hws[pll_data->onecell_idx] =3D = hw; > > + } > > + > > + /* Register fixed dividers */ > > + hw =3D clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL1_DIV2= , > > + NPCM8XX_CLK_S_PLL1, 0, 1, 2); > > + if (IS_ERR(hw)) { > > + pr_err("npcm8xx_clk: Can't register fixed div\n"); > > + goto npcm8xx_init_fail; > > + } > > + > > + hw =3D clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PLL2_DIV2= , > > + NPCM8XX_CLK_S_PLL2, 0, 1, 2); > > + if (IS_ERR(hw)) { > > + pr_err("npcm8xx_clk: Can't register pll div2\n"); > > + goto npcm8xx_init_fail; > > + } > > + > > + hw =3D clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_PRE_CLK, > > + NPCM8XX_CLK_S_CPU_MUX, 0, 1, 2)= ; > > + if (IS_ERR(hw)) { > > + pr_err("npcm8xx_clk: Can't register ckclk div2\n"); > > + goto npcm8xx_init_fail; > > + } > > + > > + hw =3D clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_AXI, > > + NPCM8XX_CLK_S_TH, 0, 1, 2); > > + if (IS_ERR(hw)) { > > + pr_err("npcm8xx_clk: Can't register axi div2\n"); > > + goto npcm8xx_init_fail; > > + } > > + > > + hw =3D clk_hw_register_fixed_factor(NULL, NPCM8XX_CLK_S_ATB, > > + NPCM8XX_CLK_S_AXI, 0, 1, 2); > > + if (IS_ERR(hw)) { > > + pr_err("npcm8xx_clk: Can't register atb div2\n"); > > + goto npcm8xx_init_fail; > > + } > > + > > + /* Register muxes */ > > + for (i =3D 0; i < ARRAY_SIZE(npcm8xx_muxes); i++) { > > + const struct npcm8xx_clk_mux_data *mux_data =3D > &npcm8xx_muxes[i]; > > + > > + hw =3D clk_hw_register_mux_table(NULL, mux_data->name, > > + mux_data->parent_names, > > + mux_data->num_parents, > > + mux_data->flags, > > + clk_base + NPCM8XX_CLKSEL, > > + mux_data->shift, > > + mux_data->mask, 0, > > + mux_data->table, > > + &npcm8xx_clk_lock); > > + > > + if (IS_ERR(hw)) { > > + pr_err("npcm8xx_clk: Can't register mux\n"); > > + goto npcm8xx_init_fail; > > + } > > + > > + if (mux_data->onecell_idx >=3D 0) > > + npcm8xx_clk_data->hws[mux_data->onecell_idx] =3D = hw; > > + } > > + > > + /* Register clock dividers specified in npcm8xx_divs */ > > + for (i =3D 0; i < ARRAY_SIZE(npcm8xx_divs); i++) { > > + const struct npcm8xx_clk_div_data *div_data =3D > &npcm8xx_divs[i]; > > + > > + hw =3D clk_hw_register_divider(NULL, div_data->name, > > + div_data->parent_name, > > + div_data->flags, > > + clk_base + div_data->reg, > > + div_data->shift, > div_data->width, > > + div_data->clk_divider_flags, > > + &npcm8xx_clk_lock); > > + if (IS_ERR(hw)) { > > + pr_err("npcm8xx_clk: Can't register div table\n")= ; > > + goto npcm8xx_init_fail; > > + } > > + > > + if (div_data->onecell_idx >=3D 0) > > + npcm8xx_clk_data->hws[div_data->onecell_idx] =3D = hw; > > + } > > + > > + ret =3D of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, > > + npcm8xx_clk_data); > > + if (ret) > > + pr_err("failed to add DT provider: %d\n", ret); > > + > > + of_node_put(clk_np); > > + > > + return; > > + > > +npcm8xx_init_fail: > > + kfree(npcm8xx_clk_data->hws); > > +npcm8xx_init_np_err: > > + iounmap(clk_base); > > +npcm8xx_init_error: > > + of_node_put(clk_np); > > +} > > + > > +CLK_OF_DECLARE(npcm8xx_clk_init, "nuvoton,npcm845-clk", > npcm8xx_clk_init); > > > > -- > i. > > Best regards, Tomer --000000000000b6847e05dfad428a Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi=C2=A0Ilpo,

<= /div>
Thanks for your comments.

<= /div>
the patch will=C2=A0modify according to your comments= and will be sent in the next kernel revision 5.19.rc1

=
On Mon, 23= May 2022 at 10:07, Ilpo J=C3=A4rvinen <ilpo.jarvinen@linux.intel.com> wr= ote:
On Sun, 22 = May 2022, Tomer Maimon wrote:

> Nuvoton Arbel BMC NPCM7XX contains an integrated clock controller, whi= ch
> generates and supplies clocks to all modules within the BMC.
>
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>

> +static struct clk_hw *
> +npcm8xx_clk_register_pll(void __iomem *pllcon, const char *name,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 const char *parent_name, unsigned long flags)
> +{
> +=C2=A0 =C2=A0 =C2=A0struct npcm8xx_clk_pll *pll;
> +=C2=A0 =C2=A0 =C2=A0struct clk_init_data init;
> +=C2=A0 =C2=A0 =C2=A0struct clk_hw *hw;
> +=C2=A0 =C2=A0 =C2=A0int ret;
> +
> +=C2=A0 =C2=A0 =C2=A0pll =3D kzalloc(sizeof(*pll), GFP_KERNEL);
> +=C2=A0 =C2=A0 =C2=A0if (!pll)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return ERR_PTR(-ENOME= M);
> +
> +=C2=A0 =C2=A0 =C2=A0pr_debug("%s reg, name=3D%s, p=3D%s\n",= __func__, name, parent_name);
> +
> +=C2=A0 =C2=A0 =C2=A0init.name =3D name;
> +=C2=A0 =C2=A0 =C2=A0init.ops =3D &npcm8xx_clk_pll_ops;
> +=C2=A0 =C2=A0 =C2=A0init.parent_names =3D &parent_name;
> +=C2=A0 =C2=A0 =C2=A0init.num_parents =3D 1;
> +=C2=A0 =C2=A0 =C2=A0init.flags =3D flags;
> +
> +=C2=A0 =C2=A0 =C2=A0pll->pllcon =3D pllcon;
> +=C2=A0 =C2=A0 =C2=A0pll->hw.init =3D &init;
> +
> +=C2=A0 =C2=A0 =C2=A0hw =3D &pll->hw;
> +
> +=C2=A0 =C2=A0 =C2=A0ret =3D clk_hw_register(NULL, hw);
> +=C2=A0 =C2=A0 =C2=A0if (ret) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0kfree(pll);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hw =3D ERR_PTR(ret);<= br> > +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0return hw;
> +}
> +
> +#define NPCM8XX_CLKEN1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x00)
> +#define NPCM8XX_CLKEN2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x28)
> +#define NPCM8XX_CLKEN3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x30)
> +#define NPCM8XX_CLKEN4=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x70)
> +#define NPCM8XX_CLKSEL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x04)
> +#define NPCM8XX_CLKDIV1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x08)
> +#define NPCM8XX_CLKDIV2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x2C)
> +#define NPCM8XX_CLKDIV3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x58)
> +#define NPCM8XX_CLKDIV4=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x7C)
> +#define NPCM8XX_PLLCON0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x0C)
> +#define NPCM8XX_PLLCON1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x10)
> +#define NPCM8XX_PLLCON2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x54)
> +#define NPCM8XX_SWRSTR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x14)
> +#define NPCM8XX_IRQWAKECON=C2=A0 =C2=A0 =C2=A0 (0x18)
> +#define NPCM8XX_IRQWAKEFLAG=C2=A0 =C2=A0 =C2=A0(0x1C)
> +#define NPCM8XX_IPSRST1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x20)
> +#define NPCM8XX_IPSRST2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x24)
> +#define NPCM8XX_IPSRST3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x34)
> +#define NPCM8XX_WD0RCR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x38)
> +#define NPCM8XX_WD1RCR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x3C)
> +#define NPCM8XX_WD2RCR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x40)
> +#define NPCM8XX_SWRSTC1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x44)
> +#define NPCM8XX_SWRSTC2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x48)
> +#define NPCM8XX_SWRSTC3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x4C)
> +#define NPCM8XX_SWRSTC4=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x50)
> +#define NPCM8XX_CORSTC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x5C)
> +#define NPCM8XX_PLLCONG=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x60)
> +#define NPCM8XX_AHBCKFI=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x64)
> +#define NPCM8XX_SECCNT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x68)
> +#define NPCM8XX_CNTR25M=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x6C)
> +#define NPCM8XX_THRTL_CNT=C2=A0 =C2=A0 =C2=A0 =C2=A0(0xC0)
> +
> +struct npcm8xx_clk_gate_data {
> +=C2=A0 =C2=A0 =C2=A0u32 reg;
> +=C2=A0 =C2=A0 =C2=A0u8 bit_idx;
> +=C2=A0 =C2=A0 =C2=A0const char *name;
> +=C2=A0 =C2=A0 =C2=A0const char *parent_name;
> +=C2=A0 =C2=A0 =C2=A0unsigned long flags;
> +=C2=A0 =C2=A0 =C2=A0/*
> +=C2=A0 =C2=A0 =C2=A0 * If this clock is exported via DT, set onecell_= idx to constant
> +=C2=A0 =C2=A0 =C2=A0 * defined in include/dt-bindings/clock/nuvoton, = NPCM8XX-clock.h for
> +=C2=A0 =C2=A0 =C2=A0 * this specific clock.=C2=A0 Otherwise, set to -= 1.
> +=C2=A0 =C2=A0 =C2=A0 */
> +=C2=A0 =C2=A0 =C2=A0int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_mux_data {
> +=C2=A0 =C2=A0 =C2=A0u8 shift;
> +=C2=A0 =C2=A0 =C2=A0u8 mask;
> +=C2=A0 =C2=A0 =C2=A0u32 *table;
> +=C2=A0 =C2=A0 =C2=A0const char *name;
> +=C2=A0 =C2=A0 =C2=A0const char * const *parent_names;
> +=C2=A0 =C2=A0 =C2=A0u8 num_parents;
> +=C2=A0 =C2=A0 =C2=A0unsigned long flags;
> +=C2=A0 =C2=A0 =C2=A0/*
> +=C2=A0 =C2=A0 =C2=A0 * If this clock is exported via DT, set onecell_= idx to constant
> +=C2=A0 =C2=A0 =C2=A0 * defined in include/dt-bindings/clock/nuvoton, = NPCM8XX-clock.h for
> +=C2=A0 =C2=A0 =C2=A0 * this specific clock.=C2=A0 Otherwise, set to -= 1.
> +=C2=A0 =C2=A0 =C2=A0 */
> +=C2=A0 =C2=A0 =C2=A0int onecell_idx;
> +
> +};
> +
> +struct npcm8xx_clk_div_fixed_data {
> +=C2=A0 =C2=A0 =C2=A0u8 mult;
> +=C2=A0 =C2=A0 =C2=A0u8 div;
> +=C2=A0 =C2=A0 =C2=A0const char *name;
> +=C2=A0 =C2=A0 =C2=A0const char *parent_name;
> +=C2=A0 =C2=A0 =C2=A0u8 clk_divider_flags;
> +=C2=A0 =C2=A0 =C2=A0/*
> +=C2=A0 =C2=A0 =C2=A0 * If this clock is exported via DT, set onecell_= idx to constant
> +=C2=A0 =C2=A0 =C2=A0 * defined in include/dt-bindings/clock/nuvoton, = NPCM8XX-clock.h for
> +=C2=A0 =C2=A0 =C2=A0 * this specific clock.=C2=A0 Otherwise, set to -= 1.
> +=C2=A0 =C2=A0 =C2=A0 */
> +=C2=A0 =C2=A0 =C2=A0int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_div_data {
> +=C2=A0 =C2=A0 =C2=A0u32 reg;
> +=C2=A0 =C2=A0 =C2=A0u8 shift;
> +=C2=A0 =C2=A0 =C2=A0u8 width;
> +=C2=A0 =C2=A0 =C2=A0const char *name;
> +=C2=A0 =C2=A0 =C2=A0const char *parent_name;
> +=C2=A0 =C2=A0 =C2=A0u8 clk_divider_flags;
> +=C2=A0 =C2=A0 =C2=A0unsigned long flags;
> +=C2=A0 =C2=A0 =C2=A0/*
> +=C2=A0 =C2=A0 =C2=A0 * If this clock is exported via DT, set onecell_= idx to constant
> +=C2=A0 =C2=A0 =C2=A0 * defined in include/dt-bindings/clock/nuvoton, = NPCM8XX-clock.h for
> +=C2=A0 =C2=A0 =C2=A0 * this specific clock.=C2=A0 Otherwise, set to -= 1.
> +=C2=A0 =C2=A0 =C2=A0 */
> +=C2=A0 =C2=A0 =C2=A0int onecell_idx;
> +};
> +
> +struct npcm8xx_clk_pll_data {
> +=C2=A0 =C2=A0 =C2=A0u32 reg;
> +=C2=A0 =C2=A0 =C2=A0const char *name;
> +=C2=A0 =C2=A0 =C2=A0const char *parent_name;
> +=C2=A0 =C2=A0 =C2=A0unsigned long flags;
> +=C2=A0 =C2=A0 =C2=A0/*
> +=C2=A0 =C2=A0 =C2=A0 * If this clock is exported via DT, set onecell_= idx to constant
> +=C2=A0 =C2=A0 =C2=A0 * defined in include/dt-bindings/clock/nuvoton, = NPCM8XX-clock.h for
> +=C2=A0 =C2=A0 =C2=A0 * this specific clock.=C2=A0 Otherwise, set to -= 1.
> +=C2=A0 =C2=A0 =C2=A0 */
> +=C2=A0 =C2=A0 =C2=A0int onecell_idx;
> +};
> +


> +/*
> + * Single copy of strings used to refer to clocks within this driver = indexed by
> + * above enum.
> + */
> +#define NPCM8XX_CLK_S_REFCLK=C2=A0 =C2=A0 =C2=A0 "refclk" > +#define NPCM8XX_CLK_S_SYSBYPCK=C2=A0 =C2=A0 "sysbypck"
> +#define NPCM8XX_CLK_S_MCBYPCK=C2=A0 =C2=A0 =C2=A0"mcbypck"<= br> > +#define NPCM8XX_CLK_S_GFXBYPCK=C2=A0 =C2=A0 "gfxbypck"
> +#define NPCM8XX_CLK_S_PLL0=C2=A0 =C2=A0 =C2=A0 =C2=A0 "pll0"= ;
> +#define NPCM8XX_CLK_S_PLL1=C2=A0 =C2=A0 =C2=A0 =C2=A0 "pll1"= ;
> +#define NPCM8XX_CLK_S_PLL1_DIV2=C2=A0 =C2=A0"pll1_div2"
> +#define NPCM8XX_CLK_S_PLL2=C2=A0 =C2=A0 =C2=A0 =C2=A0 "pll2"= ;
> +#define NPCM8XX_CLK_S_PLL_GFX=C2=A0 =C2=A0 =C2=A0"pll_gfx"<= br> > +#define NPCM8XX_CLK_S_PLL2_DIV2=C2=A0 =C2=A0"pll2_div2"
> +#define NPCM8XX_CLK_S_PIX_MUX=C2=A0 =C2=A0 =C2=A0"gfx_pixel"= ;
> +#define NPCM8XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
> +#define NPCM8XX_CLK_S_MC_MUX=C2=A0 =C2=A0 =C2=A0 "mc_phy" > +#define NPCM8XX_CLK_S_CPU_MUX=C2=A0 =C2=A0 =C2=A0"cpu"=C2= =A0 /*AKA system clock.*/

Add spaces around comment.

> +#define NPCM8XX_CLK_S_MC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "mc&q= uot;
> +#define NPCM8XX_CLK_S_AXI=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"axi&= quot;=C2=A0 /*AKA CLK2*/
> +#define NPCM8XX_CLK_S_AHB=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"ahb&= quot;=C2=A0 /*AKA CLK4*/

Ditto.

> +static void __init npcm8xx_clk_init(struct device_node *clk_np)
> +{
> +=C2=A0 =C2=A0 =C2=A0struct clk_hw_onecell_data *npcm8xx_clk_data;
> +=C2=A0 =C2=A0 =C2=A0void __iomem *clk_base;
> +=C2=A0 =C2=A0 =C2=A0struct resource res;
> +=C2=A0 =C2=A0 =C2=A0struct clk_hw *hw;
> +=C2=A0 =C2=A0 =C2=A0int ret;
> +=C2=A0 =C2=A0 =C2=A0int i;
> +
> +=C2=A0 =C2=A0 =C2=A0ret =3D of_address_to_resource(clk_np, 0, &re= s);
> +=C2=A0 =C2=A0 =C2=A0if (ret) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pr_err("%pOFn: f= ailed to get resource, ret %d\n", clk_np, ret);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return;
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0clk_base =3D ioremap(res.start, resource_size(&am= p;res));
> +=C2=A0 =C2=A0 =C2=A0if (!clk_base)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto npcm8xx_init_err= or;
> +
> +=C2=A0 =C2=A0 =C2=A0npcm8xx_clk_data =3D kzalloc(struct_size(npcm8xx_= clk_data, hws,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 NPCM8XX_NUM_CLOCKS), GFP_KERNEL);
> +=C2=A0 =C2=A0 =C2=A0if (!npcm8xx_clk_data)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto npcm8xx_init_np_= err;
> +
> +=C2=A0 =C2=A0 =C2=A0npcm8xx_clk_data->num =3D NPCM8XX_NUM_CLOCKS;<= br> > +
> +=C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < NPCM8XX_NUM_CLOCKS; i++)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0npcm8xx_clk_data->= hws[i] =3D ERR_PTR(-EPROBE_DEFER);
> +
> +=C2=A0 =C2=A0 =C2=A0/* Register plls */
> +=C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < ARRAY_SIZE(npcm8xx_plls); i+= +) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0const struct npcm8xx_= clk_pll_data *pll_data =3D &npcm8xx_plls[i];
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hw =3D npcm8xx_clk_re= gister_pll(clk_base + pll_data->reg,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0pll_data->name,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0pll_data->parent_name,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0pll_data->flags);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (IS_ERR(hw)) {

Who deregisters the already registered plls on error paths?

You might want to consider devm_ variants in npcm8xx_clk_register_pll() to =
make the cleanup simpler.

Please check the other error path rollbacks from this point onward too.=C2= =A0

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0pr_err("npcm8xx_clk: Can't register pll\n");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0goto npcm8xx_init_fail;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (pll_data->onec= ell_idx >=3D 0)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0npcm8xx_clk_data->hws[pll_data->onecell_idx] =3D hw;
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0/* Register fixed dividers */
> +=C2=A0 =C2=A0 =C2=A0hw =3D clk_hw_register_fixed_factor(NULL, NPCM8XX= _CLK_S_PLL1_DIV2,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0NPCM8= XX_CLK_S_PLL1, 0, 1, 2);
> +=C2=A0 =C2=A0 =C2=A0if (IS_ERR(hw)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pr_err("npcm8xx_= clk: Can't register fixed div\n");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto npcm8xx_init_fai= l;
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0hw =3D clk_hw_register_fixed_factor(NULL, NPCM8XX= _CLK_S_PLL2_DIV2,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0NPCM8= XX_CLK_S_PLL2, 0, 1, 2);
> +=C2=A0 =C2=A0 =C2=A0if (IS_ERR(hw)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pr_err("npcm8xx_= clk: Can't register pll div2\n");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto npcm8xx_init_fai= l;
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0hw =3D clk_hw_register_fixed_factor(NULL, NPCM8XX= _CLK_S_PRE_CLK,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0NPCM8= XX_CLK_S_CPU_MUX, 0, 1, 2);
> +=C2=A0 =C2=A0 =C2=A0if (IS_ERR(hw)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pr_err("npcm8xx_= clk: Can't register ckclk div2\n");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto npcm8xx_init_fai= l;
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0hw =3D clk_hw_register_fixed_factor(NULL, NPCM8XX= _CLK_S_AXI,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0NPCM8= XX_CLK_S_TH, 0, 1, 2);
> +=C2=A0 =C2=A0 =C2=A0if (IS_ERR(hw)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pr_err("npcm8xx_= clk: Can't register axi div2\n");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto npcm8xx_init_fai= l;
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0hw =3D clk_hw_register_fixed_factor(NULL, NPCM8XX= _CLK_S_ATB,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0NPCM8= XX_CLK_S_AXI, 0, 1, 2);
> +=C2=A0 =C2=A0 =C2=A0if (IS_ERR(hw)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pr_err("npcm8xx_= clk: Can't register atb div2\n");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto npcm8xx_init_fai= l;
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0/* Register muxes */
> +=C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < ARRAY_SIZE(npcm8xx_muxes); i= ++) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0const struct npcm8xx_= clk_mux_data *mux_data =3D &npcm8xx_muxes[i];
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hw =3D clk_hw_registe= r_mux_table(NULL, mux_data->name,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 mux_data->parent_names,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 mux_data->num_parents,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 mux_data->flags,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 clk_base + NPCM8XX_CLKSEL,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 mux_data->shift,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 mux_data->mask, 0,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 mux_data->table,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 &npcm8xx_clk_lock);
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (IS_ERR(hw)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0pr_err("npcm8xx_clk: Can't register mux\n");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0goto npcm8xx_init_fail;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (mux_data->onec= ell_idx >=3D 0)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0npcm8xx_clk_data->hws[mux_data->onecell_idx] =3D hw;
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0/* Register clock dividers specified in npcm8xx_d= ivs */
> +=C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < ARRAY_SIZE(npcm8xx_divs); i+= +) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0const struct npcm8xx_= clk_div_data *div_data =3D &npcm8xx_divs[i];
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hw =3D clk_hw_registe= r_divider(NULL, div_data->name,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 div_data->parent_name,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 div_data->flags,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 clk_base + div_data->reg,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 div_data->shift, div_data->width,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 div_data->clk_divider_flags,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 &npcm8xx_clk_lock);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (IS_ERR(hw)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0pr_err("npcm8xx_clk: Can't register div table\n");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0goto npcm8xx_init_fail;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (div_data->onec= ell_idx >=3D 0)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0npcm8xx_clk_data->hws[div_data->onecell_idx] =3D hw;
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0ret =3D of_clk_add_hw_provider(clk_np, of_clk_hw_= onecell_get,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 npcm8xx_clk_data);
> +=C2=A0 =C2=A0 =C2=A0if (ret)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pr_err("failed t= o add DT provider: %d\n", ret);
> +
> +=C2=A0 =C2=A0 =C2=A0of_node_put(clk_np);
> +
> +=C2=A0 =C2=A0 =C2=A0return;
> +
> +npcm8xx_init_fail:
> +=C2=A0 =C2=A0 =C2=A0kfree(npcm8xx_clk_data->hws);
> +npcm8xx_init_np_err:
> +=C2=A0 =C2=A0 =C2=A0iounmap(clk_base);
> +npcm8xx_init_error:
> +=C2=A0 =C2=A0 =C2=A0of_node_put(clk_np);
> +}
> +
> +CLK_OF_DECLARE(npcm8xx_clk_init, "nuvoton,npcm845-clk", npc= m8xx_clk_init);
>

--
=C2=A0i.


Best regards,

Tomer=C2=A0
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