Hi Rob,

On Thu, 3 Jan 2019 at 23:14, Rob Herrin= g <robh@kernel.org> wrote:
=

On Mon, Dec 24, 201= 8 at 06:47:54PM +0200, Tomer Maimon wrote:
> Added device tree binding documentation for Nuvoton BMC
> NPCM Analog-to-Digital Converter(ADC).
>
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>=C2=A0 .../bindings/iio/adc/nuvoton,npcm-adc.txt=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 | 35 ++++++++++++++++++++++
>=C2=A0 1 file changed, 35 insertions(+)
>=C2=A0 create mode 100644 Documentation/devicetree/bindings/iio/adc/nuv= oton,npcm-adc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-ad= c.txt b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt
> new file mode 100644
> index 000000000000..6f0843d837cc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/nuvoton,npcm-adc.txt > @@ -0,0 +1,35 @@
> +Nuvoton NPCM Analog to Digital Converter (ADC)
> +
> +The NPCM ADC is a 10-bit converter for eight channel inputs.
> +
> +Required properties:
> +- compatible : "nuvoton,npcm750-adc" for the NPCM7XX BMC. > +- reg=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 : specifies physical base address and size of the regi= sters.
> +- interrupts : Contain the ADC interrupt with flags for falling edge.=
> +
> +Optional properties:
> +- clocks=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0: phandle of = ADC reference clock, in case the clock is not
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0added the ADC will use the defaul= t ADC sample rate.
> +- vref-supply=C2=A0 =C2=A0 =C2=A0 =C2=A0 : The regulator supply ADC r= eference voltage, in case the
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0vref-supply is not added the ADC = will use internal voltage
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0reference.
> +
> +Required Node in the NPCM7xx BMC:
> +An additional register is present in the NPCM7xx SOC which is
> +assumed to be in the same device tree, with and marked as
> +compatible with "nuvoton,npcm750-rst".
> +
> +Example:
> +
> +adc: adc@f000c000 {
> +=C2=A0 =C2=A0 =C2=A0compatible =3D "nuvoton,npcm750-adc"; > +=C2=A0 =C2=A0 =C2=A0reg =3D <0xf000c000 0x8>;
> +=C2=A0 =C2=A0 =C2=A0interrupts =3D <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH&= gt;;
> +=C2=A0 =C2=A0 =C2=A0clocks =3D <&clk NPCM7XX_CLK_ADC>;
> +};
> +
> +rst: rst@f0801000 {

Why is this node here?

example for the reset node that= required when using NPCM7xx SOC.

(Required Node in the NPCM7xx B= MC:

An additional register is present in the NPCM7xx SOC which is
a= ssumed to be in the same device tree, with and marked as
compatible with= "nuvoton,npcm750-rst")

> +=C2=A0 =C2=A0 =C2=A0compatible =3D "nuvoton,npcm750-rst", &= quot;syscon",
> +=C2=A0 =C2=A0 =C2=A0"simple-mfd";
> +=C2=A0 =C2=A0 =C2=A0reg =3D <0xf0801000 0x6C>;
> +};
> --
> 2.14.1
>

Thanks,

= Tomer=C2=A0