Hi Philipp,

Thanks a l= ot for your comments.

On Tue, 29 Oct 2019 at 17:34= , Philipp Zabel <p.zabel@pengu= tronix.de> wrote:

On Mon, 2019-10-28 at 17:54 +0200= , Tomer Maimon wrote:
> Add Nuvoton NPCM BMC reset controller driver.
>
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>=C2=A0 drivers/reset/Kconfig=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A07 +
>=C2=A0 drivers/reset/Makefile=C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A01 +
>=C2=A0 drivers/reset/reset-npcm.c | 275 +++++++++++++++++++++++++++++++= ++++++
>=C2=A0 3 files changed, 283 insertions(+)
>=C2=A0 create mode 100644 drivers/reset/reset-npcm.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 7b07281aa0ae..5dbfdf6d717a 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -89,6 +89,13 @@ config RESET_MESON_AUDIO_ARB
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0This enables the reset driver for Aud= io Memory Arbiter of
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Amlogic's A113 based SoCs
>=C2=A0
> +config RESET_NPCM
> +=C2=A0 =C2=A0 =C2=A0bool "NPCM BMC Reset Driver"
> +=C2=A0 =C2=A0 =C2=A0depends on ARCH_NPCM || COMPILE_TEST
> +=C2=A0 =C2=A0 =C2=A0help
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0This enables the reset controller driver f= or Nuvoton NPCM
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0BMC SoCs.
> +

Is there any reason to ever disable this driver when building ARCH_NPCM?
>=C2=A0 config RESET_OXNAS
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool
>=C2=A0
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index cf60ce526064..00767c03f5f2 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LANTIQ) +=3D reset-lantiq.o
>=C2=A0 obj-$(CONFIG_RESET_LPC18XX) +=3D reset-lpc18xx.o
>=C2=A0 obj-$(CONFIG_RESET_MESON) +=3D reset-meson.o
>=C2=A0 obj-$(CONFIG_RESET_MESON_AUDIO_ARB) +=3D reset-meson-audio-arb.o=
> +obj-$(CONFIG_RESET_NPCM) +=3D reset-npcm.o
>=C2=A0 obj-$(CONFIG_RESET_OXNAS) +=3D reset-oxnas.o
>=C2=A0 obj-$(CONFIG_RESET_PISTACHIO) +=3D reset-pistachio.o
>=C2=A0 obj-$(CONFIG_RESET_QCOM_AOSS) +=3D reset-qcom-aoss.o
> diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c > new file mode 100644
> index 000000000000..ebb3071767e1
> --- /dev/null
> +++ b/drivers/reset/reset-npcm.c
> @@ -0,0 +1,275 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2019 Nuvoton Technology corporation.
> +
> +#include <linux/clk.h>

Please remove unused header includes.

> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/init.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reboot.h>
> +#include <linux/reset-controller.h>
> +#include <linux/spinlock.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
> +#include <linux/of_address.h>
> +
> +/* NPCM7xx GCR registers */
> +#define NPCM_MDLR_OFFSET=C2=A0 =C2=A0 =C2=A00x7C
> +#define NPCM_MDLR_USBD0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 BIT(9)
> +#define NPCM_MDLR_USBD1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 BIT(8)
> +#define NPCM_MDLR_USBD2_4=C2=A0 =C2=A0 BIT(21)
> +#define NPCM_MDLR_USBD5_9=C2=A0 =C2=A0 BIT(22)
> +
> +#define NPCM_USB1PHYCTL_OFFSET=C2=A0 =C2=A0 =C2=A0 =C2=A00x140
> +#define NPCM_USB2PHYCTL_OFFSET=C2=A0 =C2=A0 =C2=A0 =C2=A00x144
> +#define NPCM_USBXPHYCTL_RS=C2=A0 =C2=A0BIT(28)
> +
> +/* NPCM7xx Reset registers */
> +#define NPCM_SWRSTR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x14
> +#define NPCM_SWRST=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0BIT(2)
> +
> +#define NPCM_IPSRST1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x20
> +#define NPCM_IPSRST1_USBD1=C2=A0 =C2=A0BIT(5)
> +#define NPCM_IPSRST1_USBD2=C2=A0 =C2=A0BIT(8)
> +#define NPCM_IPSRST1_USBD3=C2=A0 =C2=A0BIT(25)
> +#define NPCM_IPSRST1_USBD4=C2=A0 =C2=A0BIT(22)
> +#define NPCM_IPSRST1_USBD5=C2=A0 =C2=A0BIT(23)
> +#define NPCM_IPSRST1_USBD6=C2=A0 =C2=A0BIT(24)
> +
> +#define NPCM_IPSRST2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x24
> +#define NPCM_IPSRST2_USB_HOST=C2=A0 =C2=A0 =C2=A0 =C2=A0 BIT(26)
> +
> +#define NPCM_IPSRST3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x34
> +#define NPCM_IPSRST3_USBD0=C2=A0 =C2=A0BIT(4)
> +#define NPCM_IPSRST3_USBD7=C2=A0 =C2=A0BIT(5)
> +#define NPCM_IPSRST3_USBD8=C2=A0 =C2=A0BIT(6)
> +#define NPCM_IPSRST3_USBD9=C2=A0 =C2=A0BIT(7)
> +#define NPCM_IPSRST3_USBPHY1 BIT(24)
> +#define NPCM_IPSRST3_USBPHY2 BIT(25)
> +
> +#define NPCM_RC_RESETS_PER_REG=C2=A0 =C2=A0 =C2=A0 =C2=A032
> +
> +struct npcm_rc_data {
> +=C2=A0 =C2=A0 =C2=A0struct reset_controller_dev rcdev;
> +=C2=A0 =C2=A0 =C2=A0struct notifier_block restart_nb;
> +=C2=A0 =C2=A0 =C2=A0u32 sw_reset_number;
> +=C2=A0 =C2=A0 =C2=A0void __iomem *base;
> +=C2=A0 =C2=A0 =C2=A0spinlock_t lock;
> +};
> +
> +#define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev)
> +
> +static int npcm_rc_restart(struct notifier_block *nb, unsigned long m= ode,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 void *cmd)
> +{
> +=C2=A0 =C2=A0 =C2=A0struct npcm_rc_data *rc =3D container_of(nb, stru= ct npcm_rc_data,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 restart_nb);
> +
> +=C2=A0 =C2=A0 =C2=A0writel(NPCM_SWRST << rc->sw_reset_number= , rc->base + NPCM_SWRSTR);
> +=C2=A0 =C2=A0 =C2=A0mdelay(1000);
> +
> +=C2=A0 =C2=A0 =C2=A0pr_emerg("%s: unable to restart system\n&quo= t;, __func__);
> +
> +=C2=A0 =C2=A0 =C2=A0return NOTIFY_DONE;
> +}
> +
> +static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev,=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0unsigned long id, bool set)
> +{
> +=C2=A0 =C2=A0 =C2=A0struct npcm_rc_data *rc =3D to_rc_data(rcdev); > +=C2=A0 =C2=A0 =C2=A0u32 ctrl_offset =3D NPCM_IPSRST1;
> +=C2=A0 =C2=A0 =C2=A0unsigned long flags;
> +=C2=A0 =C2=A0 =C2=A0u32 stat, rst_bit;
> +
> +=C2=A0 =C2=A0 =C2=A0ctrl_offset +=3D (id / NPCM_RC_RESETS_PER_REG) * = sizeof(u32);
> +=C2=A0 =C2=A0 =C2=A0rst_bit =3D 1 << (id % NPCM_RC_RESETS_PER_R= EG);
> +
> +=C2=A0 =C2=A0 =C2=A0spin_lock_irqsave(&rc->lock, flags);
> +=C2=A0 =C2=A0 =C2=A0stat =3D readl(rc->base + ctrl_offset);
> +=C2=A0 =C2=A0 =C2=A0if (set)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0writel(stat | rst_bit= , rc->base + ctrl_offset);
> +=C2=A0 =C2=A0 =C2=A0else
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0writel(stat & ~rs= t_bit, rc->base + ctrl_offset);
> +=C2=A0 =C2=A0 =C2=A0spin_unlock_irqrestore(&rc->lock, flags);<= br> > +
> +=C2=A0 =C2=A0 =C2=A0return 0;
> +}
> +
> +static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigne= d long id)
> +{
> +=C2=A0 =C2=A0 =C2=A0return npcm_rc_setclear_reset(rcdev, id, true); > +}
> +
> +static int npcm_rc_deassert(struct reset_controller_dev *rcdev,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0unsigned long id)
> +{
> +=C2=A0 =C2=A0 =C2=A0return npcm_rc_setclear_reset(rcdev, id, false);<= br> > +}
> +
> +static int npcm_rc_status(struct reset_controller_dev *rcdev,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0unsigned long id)
> +{
> +=C2=A0 =C2=A0 =C2=A0struct npcm_rc_data *rc =3D to_rc_data(rcdev); > +=C2=A0 =C2=A0 =C2=A0u32 bit, ctrl_offset =3D NPCM_IPSRST1;
> +
> +=C2=A0 =C2=A0 =C2=A0ctrl_offset +=3D (id / NPCM_RC_RESETS_PER_REG) * = sizeof(u32);
> +=C2=A0 =C2=A0 =C2=A0bit =3D 1 << (id % NPCM_RC_RESETS_PER_REG);=
> +
> +=C2=A0 =C2=A0 =C2=A0return (readl(rc->base + ctrl_offset) & bi= t);
> +}
> +
> +/*
> + *=C2=A0 The following procedure should be observed in USB PHY, USB d= evice and
> + *=C2=A0 USB host initialization at BMC boot
> + */
> +static int npcm_usb_reset(struct platform_device *pdev, struct npcm_r= c_data *rc)
> +{
> +=C2=A0 =C2=A0 =C2=A0struct device_node *np =3D pdev->dev.of_node;<= br> > +=C2=A0 =C2=A0 =C2=A0u32 mdlr, iprst1, iprst2, iprst3;
> +=C2=A0 =C2=A0 =C2=A0struct regmap *gcr_regmap;
> +=C2=A0 =C2=A0 =C2=A0u32 ipsrst1_bits =3D 0;
> +=C2=A0 =C2=A0 =C2=A0u32 ipsrst2_bits =3D NPCM_IPSRST2_USB_HOST;
> +=C2=A0 =C2=A0 =C2=A0u32 ipsrst3_bits =3D 0;
> +
> +=C2=A0 =C2=A0 =C2=A0if (of_device_is_compatible(np, "nuvoton,npc= m750-reset")) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gcr_regmap =3D syscon= _regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (IS_ERR(gcr_regmap= )) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr\= n");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0return PTR_ERR(gcr_regmap);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> +=C2=A0 =C2=A0 =C2=A0}
> +=C2=A0 =C2=A0 =C2=A0if (!gcr_regmap)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -ENXIO;
> +
> +=C2=A0 =C2=A0 =C2=A0/* checking which USB device is enabled */
> +=C2=A0 =C2=A0 =C2=A0regmap_read(gcr_regmap, NPCM_MDLR_OFFSET, &md= lr);
> +=C2=A0 =C2=A0 =C2=A0if (!(mdlr & NPCM_MDLR_USBD0))
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ipsrst3_bits |=3D NPC= M_IPSRST3_USBD0;
> +=C2=A0 =C2=A0 =C2=A0if (!(mdlr & NPCM_MDLR_USBD1))
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ipsrst1_bits |=3D NPC= M_IPSRST1_USBD1;
> +=C2=A0 =C2=A0 =C2=A0if (!(mdlr & NPCM_MDLR_USBD2_4))
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ipsrst1_bits |=3D (NP= CM_IPSRST1_USBD2 |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NPCM_IPSRST1_USBD3 |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NPCM_IPSRST1_USBD4);
> +=C2=A0 =C2=A0 =C2=A0if (!(mdlr & NPCM_MDLR_USBD0)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ipsrst1_bits |=3D (NP= CM_IPSRST1_USBD5 |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NPCM_IPSRST1_USBD6);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ipsrst3_bits |=3D (NP= CM_IPSRST3_USBD7 |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NPCM_IPSRST3_USBD8 |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NPCM_IPSRST3_USBD9);
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0/* assert reset USB PHY and USB devices */
> +=C2=A0 =C2=A0 =C2=A0iprst1 =3D readl(rc->base + NPCM_IPSRST1);
> +=C2=A0 =C2=A0 =C2=A0iprst2 =3D readl(rc->base + NPCM_IPSRST2);
> +=C2=A0 =C2=A0 =C2=A0iprst3 =3D readl(rc->base + NPCM_IPSRST3);
> +
> +=C2=A0 =C2=A0 =C2=A0iprst1 |=3D ipsrst1_bits;
> +=C2=A0 =C2=A0 =C2=A0iprst2 |=3D ipsrst2_bits;
> +=C2=A0 =C2=A0 =C2=A0iprst3 |=3D (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 = |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NPCM_IPSRST3_= USBPHY2);
> +
> +=C2=A0 =C2=A0 =C2=A0writel(iprst1, rc->base + NPCM_IPSRST1);
> +=C2=A0 =C2=A0 =C2=A0writel(iprst2, rc->base + NPCM_IPSRST2);
> +=C2=A0 =C2=A0 =C2=A0writel(iprst3, rc->base + NPCM_IPSRST3);
> +
> +=C2=A0 =C2=A0 =C2=A0/* clear USB PHY RS bit */
> +=C2=A0 =C2=A0 =C2=A0regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OF= FSET,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 NPCM_USBXPHYCTL_RS, 0);
> +=C2=A0 =C2=A0 =C2=A0regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OF= FSET,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 NPCM_USBXPHYCTL_RS, 0);
> +
> +=C2=A0 =C2=A0 =C2=A0/* deassert reset USB PHY */
> +=C2=A0 =C2=A0 =C2=A0iprst3 &=3D ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPS= RST3_USBPHY2);
> +=C2=A0 =C2=A0 =C2=A0writel(iprst3, rc->base + NPCM_IPSRST3);
> +
> +=C2=A0 =C2=A0 =C2=A0udelay(50);
> +
> +=C2=A0 =C2=A0 =C2=A0/* set USB PHY RS bit */
> +=C2=A0 =C2=A0 =C2=A0regmap_update_bits(gcr_regmap, NPCM_USB1PHYCTL_OF= FSET,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
> +=C2=A0 =C2=A0 =C2=A0regmap_update_bits(gcr_regmap, NPCM_USB2PHYCTL_OF= FSET,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
> +
> +=C2=A0 =C2=A0 =C2=A0/* deassert reset USB devices*/
> +=C2=A0 =C2=A0 =C2=A0iprst1 &=3D ~ipsrst1_bits;
> +=C2=A0 =C2=A0 =C2=A0iprst2 &=3D ~ipsrst2_bits;
> +=C2=A0 =C2=A0 =C2=A0iprst3 &=3D ~ipsrst3_bits;
> +
> +=C2=A0 =C2=A0 =C2=A0writel(iprst1, rc->base + NPCM_IPSRST1);
> +=C2=A0 =C2=A0 =C2=A0writel(iprst2, rc->base + NPCM_IPSRST2);
> +=C2=A0 =C2=A0 =C2=A0writel(iprst3, rc->base + NPCM_IPSRST3);
> +
> +=C2=A0 =C2=A0 =C2=A0return 0;
> +}

Is there no better place for this, such as USB glue code?

= Sorry, I didn't find a proper place to add it in the USB tree.

=C2=A0

=C2=A0
<= /blockquote>
> +static const struct reset_control_ops npcm_rc_ops =3D {
> +=C2=A0 =C2=A0 =C2=A0.assert=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D npcm= _rc_assert,
> +=C2=A0 =C2=A0 =C2=A0.deassert=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D npcm_rc_d= eassert,
> +=C2=A0 =C2=A0 =C2=A0.status=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D npcm= _rc_status,
> +};
> +
> +static int npcm_rc_probe(struct platform_device *pdev)
> +{
> +=C2=A0 =C2=A0 =C2=A0struct npcm_rc_data *rc;
> +=C2=A0 =C2=A0 =C2=A0struct resource res;
> +=C2=A0 =C2=A0 =C2=A0int ret;
> +
> +=C2=A0 =C2=A0 =C2=A0rc =3D devm_kzalloc(&pdev->dev, sizeof(*rc= ), GFP_KERNEL);
> +=C2=A0 =C2=A0 =C2=A0if (!rc)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -ENOMEM;
> +
> +=C2=A0 =C2=A0 =C2=A0of_address_to_resource(pdev->dev.of_node, 0, &= amp;res);
> +=C2=A0 =C2=A0 =C2=A0rc->base =3D devm_ioremap_resource(&pdev-&= gt;dev, &res);

Can't you just use

=C2=A0 =C2=A0 =C2=A0 =C2=A0 rc->base =3D devm_platform_ioremap_resource(= pdev, 0);

here?

> +=C2=A0 =C2=A0 =C2=A0if (IS_ERR(rc->base))
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return PTR_ERR(rc->= ;base);
> +
> +=C2=A0 =C2=A0 =C2=A0spin_lock_init(&rc->lock);
> +
> +=C2=A0 =C2=A0 =C2=A0rc->rcdev.owner =3D THIS_MODULE;
> +=C2=A0 =C2=A0 =C2=A0rc->rcdev.nr_resets =3D resource_size(&res= ) / 4 * BITS_PER_LONG;

That doesn't seem right. With the ctrl_offset =3D NPCM_IPSRST1 in
npcm_rc_setclear_reset that would allow access beyond the configured
register range.

> +=C2=A0 =C2=A0 =C2=A0rc->rcdev.ops =3D &npcm_rc_ops;
> +=C2=A0 =C2=A0 =C2=A0rc->rcdev.of_node =3D pdev->dev.of_node; > +
> +=C2=A0 =C2=A0 =C2=A0platform_set_drvdata(pdev, rc);
> +
> +=C2=A0 =C2=A0 =C2=A0ret =3D reset_controller_register(&rc->rcd= ev);

=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D devm_reset_controller_register(&pde= v->dev, &rc->rcdev);

> +=C2=A0 =C2=A0 =C2=A0if (ret) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev->= ;dev, "unable to register device\n");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0if (npcm_usb_reset(pdev, rc))
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_warn(&pdev-&g= t;dev, "NPCM USB reset failed, can cause issues with UDC and USB host\= n");
> +
> +=C2=A0 =C2=A0 =C2=A0if (!of_property_read_u32(pdev->dev.of_node, &= quot;nuvoton,sw-reset-number",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&rc->sw_reset_number)) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (rc->sw_reset_n= umber && rc->sw_reset_number < 5) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0rc->restart_nb.priority =3D 192,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0rc->restart_nb.notifier_call =3D npcm_rc_restart,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0ret =3D register_restart_handler(&rc->restart_nb);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0if (ret)
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_warn(&pdev->dev, "failed= to register restart handler\n");
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> +=C2=A0 =C2=A0 =C2=A0}
> +
> +=C2=A0 =C2=A0 =C2=A0pr_info("NPCM RESET driver probed\n");<= br>
It think this is a bit verbose.

> +=C2=A0 =C2=A0 =C2=A0return ret;
> +}
> +
> +static const struct of_device_id npcm_rc_match[] =3D {
> +=C2=A0 =C2=A0 =C2=A0{ .compatible =3D "nuvoton,npcm750-reset&quo= t; },
> +=C2=A0 =C2=A0 =C2=A0{ }
> +};
> +
> +static struct platform_driver npcm_rc_driver =3D {
> +=C2=A0 =C2=A0 =C2=A0.probe=C2=A0 =3D npcm_rc_probe,
> +=C2=A0 =C2=A0 =C2=A0.driver =3D {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.name=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D "npcm-reset= ",
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.of_match_table=C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D npcm_rc_match,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.suppress_bind_attrs= =C2=A0 =C2=A0 =3D true,
> +=C2=A0 =C2=A0 =C2=A0},
> +};
> +builtin_platform_driver(npcm_rc_driver);

regards
Philipp

Regards,

Tome= r=C2=A0