From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1845C433EF for ; Mon, 23 May 2022 14:03:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id AB31DC34100; Mon, 23 May 2022 14:03:36 +0000 (UTC) Received: from mail-yb1-f181.google.com (mail-yb1-f181.google.com [209.85.219.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 42475C385A9; Mon, 23 May 2022 14:03:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 42475C385A9 Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yb1-f181.google.com with SMTP id q135so25578753ybg.10; Mon, 23 May 2022 07:03:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=O90ohhie27d4nsRVO1889296fM+qYxnl0MoZNM5YMmI=; b=k++/jsOBDZIn4JHOwElLzj+LcTuR4+/O69MIk9vnCfBE7IhXVgIbpXQq9cpDAuJEMY 2JjN5i9lz01D0U1uaQUJ1Oi80rDsl9y58+lMaxo8F0llCWUFcgiKNirZ/INEj4YruOW6 ApcLH6EwHkl0PYqCIvWeRLxEWeMK+sa7qSzpMaRb2j9mQ/OOVYW/f9zgGI809i5JZBuS RoCX93PSclUBJFXAP3F2wKLKlrixbbSxtttj3Ew8HQbP2cXbZ1Z4bsXYGuAwAWIQaQu3 ClYvogouQmnCJA+AjGn9utRYNUH/L7qgPp2MHI37ayVMC9h0XFOemXJRzUol5iqojnuU HUyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=O90ohhie27d4nsRVO1889296fM+qYxnl0MoZNM5YMmI=; b=l8qsnb7+IGXKd+uWjs8HmxzgksIms4vB0zho6N51X3bf7wUePKYSZ4nZCfhJrTSSt7 ueI4yVz8p9T5hiZFESxiav9tdkRS03Nmq8U18rwZJtwG4Z+iTrHOjJls7vFBoOerXXSY 4RzQnshL24eS0GgK50YiEqTbQGg3sGdOE/GSoYBCcN6FuovPptzLPrj147fZOR7pXvxl 30ifxvmIkjR+n8RajZoTNWwONlH/tlfH2mBDliS3yzS3wLG/qBKz4nF9t70Rdz9Gh0TM NwMJ0sNKzmMr/2haO9ARHOvEvEKC1lbQ4thy/ib3NqJPqDOeF9DMT0zGimHS37edQJQv O/rw== X-Gm-Message-State: AOAM5333XpcUN79GQP2KaqfZpwJ1FxbANCxgznZJQtCANWO68jmahzK1 POzzGkuCQovLrrbF2taB/eaEITCx/AhZiVuPp8c= X-Google-Smtp-Source: ABdhPJzwXULST9U+Vw2XdebHSP+a3/h2knRk5rYXu/QsChOWvEH7qdAElOdS60vawDJF+RQOQVisyGeDKziGReLYWQM= X-Received: by 2002:a05:6902:70c:b0:64f:4e29:a858 with SMTP id k12-20020a056902070c00b0064f4e29a858mr18821677ybt.462.1653314614190; Mon, 23 May 2022 07:03:34 -0700 (PDT) MIME-Version: 1.0 References: <20220522155046.260146-1-tmaimon77@gmail.com> <20220522155046.260146-12-tmaimon77@gmail.com> <86cd6a37-70ad-3a90-bc8a-dcd8b41f1175@linaro.org> In-Reply-To: <86cd6a37-70ad-3a90-bc8a-dcd8b41f1175@linaro.org> From: Tomer Maimon Date: Mon, 23 May 2022 17:03:23 +0300 Message-ID: Subject: Re: [PATCH v1 11/19] dt-bindings: reset: npcm: Add support for NPCM8XX To: Krzysztof Kozlowski List-Id: Cc: Avi Fishman , Tali Perry , Joel Stanley , Patrick Venture , Nancy Yuen , Benjamin Fair , Rob Herring , krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, Philipp Zabel , Greg KH , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , catalin.marinas@arm.com, will@kernel.org, Arnd Bergmann , Olof Johansson , jirislaby@kernel.org, shawnguo@kernel.org, bjorn.andersson@linaro.org, geert+renesas@glider.be, marcel.ziswiler@toradex.com, Vinod Koul , biju.das.jz@bp.renesas.com, nobuhiro1.iwamatsu@toshiba.co.jp, robert.hancock@calian.com, =?UTF-8?Q?Jonathan_Neusch=C3=A4fer?= , lkundrak@v3.sk, soc@kernel.org, devicetree , Linux Kernel Mailing List , linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, linux-watchdog@vger.kernel.org, Linux ARM Content-Type: multipart/alternative; boundary="00000000000047e8b705dfae4eb7" --00000000000047e8b705dfae4eb7 Content-Type: text/plain; charset="UTF-8" Hi Krzysztof, Thanks for your comments. On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowski < krzysztof.kozlowski@linaro.org> wrote: > On 22/05/2022 17:50, Tomer Maimon wrote: > > Add binding document and device tree binding > > constants for Nuvoton BMC NPCM8XX reset controller. > > > > Signed-off-by: Tomer Maimon > > --- > > .../bindings/reset/nuvoton,npcm-reset.txt | 17 ++- > > .../dt-bindings/reset/nuvoton,npcm8xx-reset.h | 124 ++++++++++++++++++ > > 2 files changed, 139 insertions(+), 2 deletions(-) > > create mode 100644 include/dt-bindings/reset/nuvoton,npcm8xx-reset.h > > > > diff --git > a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt > b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt > > index cb1613092ee7..b7eb8615b68b 100644 > > --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt > > +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt > > @@ -1,14 +1,15 @@ > > Nuvoton NPCM Reset controller > > > > Required properties: > > -- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC > > +- compatible : "nuvoton,npcm750-reset" for Poleg NPCM7XX BMC. > > + "nuvoton,npcm845-reset" for Arbel NPCM8XX BMC. > > - reg : specifies physical base address and size of the register. > > - #reset-cells: must be set to 2 > > - syscon: a phandle to access GCR registers. > > > > Optional property: > > - nuvoton,sw-reset-number - Contains the software reset number to > restart the SoC. > > - NPCM7xx contain four software reset that represent numbers 1 to 4. > > + NPCM7xx and NPCM8xx contain four software reset that represent > numbers 1 to 4. > > > > If 'nuvoton,sw-reset-number' is not specified software reset is > disabled. > > > > @@ -32,3 +33,15 @@ example: > > }; > > > > The index could be found in . > > + > > +Specifying reset lines connected to IP NPCM8XX modules > > +====================================================== > > we prefer to use the same explanation as the NPCM7XX reset explanation in the reset binding document. > No need to document consumers. Just mention the header. > > > +example: > > + > > + spi0: spi@..... { > > + ... > > + resets = <&rstc NPCM8XX_RESET_IPSRST2 > NPCM8XX_RESET_PSPI1>; > > + ... > > + }; > > + > > +The index could be found in . > > diff --git a/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h > b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h > > new file mode 100644 > > index 000000000000..4b832a0fd1dd > > --- /dev/null > > +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h > > @@ -0,0 +1,124 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > Dual license. > O.K. > > > +// Copyright (c) 2022 Nuvoton Technology corporation. > > + > > +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H > > +#define _DT_BINDINGS_NPCM8XX_RESET_H > > + > > +#define NPCM8XX_RESET_IPSRST1 0x20 > > +#define NPCM8XX_RESET_IPSRST2 0x24 > > +#define NPCM8XX_RESET_IPSRST3 0x34 > > +#define NPCM8XX_RESET_IPSRST4 0x74 > > What are these? All IDs should be incremental, decimal and start from 0. > Register offset, we use the same method in NPCM7xx. please refer https://elixir.bootlin.com/linux/v5.18/source/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h and the driver asserts the reset according to the reset include definitions > > > + > > +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */ > > +#define NPCM8XX_RESET_GDMA0 3 > > IDs start from 0 and do not have holes. > This represents the reset BIT in the reset register. > > > > +#define NPCM8XX_RESET_UDC1 5 > > +#define NPCM8XX_RESET_GMAC3 6 > > +#define NPCM8XX_RESET_UART_2_3 7 > > +#define NPCM8XX_RESET_UDC2 8 > > +#define NPCM8XX_RESET_PECI 9 > > +#define NPCM8XX_RESET_AES 10 > > +#define NPCM8XX_RESET_UART_0_1 11 > > +#define NPCM8XX_RESET_MC 12 > > +#define NPCM8XX_RESET_SMB2 13 > > +#define NPCM8XX_RESET_SMB3 14 > > +#define NPCM8XX_RESET_SMB4 15 > > +#define NPCM8XX_RESET_SMB5 16 > > +#define NPCM8XX_RESET_PWM_M0 18 > > +#define NPCM8XX_RESET_TIMER_0_4 19 > > +#define NPCM8XX_RESET_TIMER_5_9 20 > > +#define NPCM8XX_RESET_GMAC4 21 > > +#define NPCM8XX_RESET_UDC4 22 > > +#define NPCM8XX_RESET_UDC5 23 > > +#define NPCM8XX_RESET_UDC6 24 > > +#define NPCM8XX_RESET_UDC3 25 > > +#define NPCM8XX_RESET_ADC 27 > > +#define NPCM8XX_RESET_SMB6 28 > > +#define NPCM8XX_RESET_SMB7 29 > > +#define NPCM8XX_RESET_SMB0 30 > > +#define NPCM8XX_RESET_SMB1 31 > > + > > +/* Reset lines on IP2 reset module (NPCM8XX_RESET_IPSRST2) */ > > +#define NPCM8XX_RESET_MFT0 0 > > +#define NPCM8XX_RESET_MFT1 1 > > +#define NPCM8XX_RESET_MFT2 2 > > +#define NPCM8XX_RESET_MFT3 3 > > +#define NPCM8XX_RESET_MFT4 4 > > +#define NPCM8XX_RESET_MFT5 5 > > +#define NPCM8XX_RESET_MFT6 6 > > +#define NPCM8XX_RESET_MFT7 7 > > +#define NPCM8XX_RESET_MMC 8 > > +#define NPCM8XX_RESET_GFX_SYS 10 > > +#define NPCM8XX_RESET_AHB_PCIBRG 11 > > +#define NPCM8XX_RESET_VDMA 12 > > +#define NPCM8XX_RESET_ECE 13 > > +#define NPCM8XX_RESET_VCD 14 > > +#define NPCM8XX_RESET_VIRUART1 16 > > +#define NPCM8XX_RESET_VIRUART2 17 > > +#define NPCM8XX_RESET_SIOX1 18 > > +#define NPCM8XX_RESET_SIOX2 19 > > +#define NPCM8XX_RESET_BT 20 > > +#define NPCM8XX_RESET_3DES 21 > > +#define NPCM8XX_RESET_PSPI2 23 > > +#define NPCM8XX_RESET_GMAC2 25 > > +#define NPCM8XX_RESET_USBH1 26 > > +#define NPCM8XX_RESET_GMAC1 28 > > +#define NPCM8XX_RESET_CP1 31 > > + > > +/* Reset lines on IP3 reset module (NPCM8XX_RESET_IPSRST3) */ > > +#define NPCM8XX_RESET_PWM_M1 0 > > +#define NPCM8XX_RESET_SMB12 1 > > +#define NPCM8XX_RESET_SPIX 2 > > +#define NPCM8XX_RESET_SMB13 3 > > +#define NPCM8XX_RESET_UDC0 4 > > +#define NPCM8XX_RESET_UDC7 5 > > +#define NPCM8XX_RESET_UDC8 6 > > +#define NPCM8XX_RESET_UDC9 7 > > +#define NPCM8XX_RESET_USBHUB 8 > > +#define NPCM8XX_RESET_PCI_MAILBOX 9 > > +#define NPCM8XX_RESET_GDMA1 10 > > +#define NPCM8XX_RESET_GDMA2 11 > > +#define NPCM8XX_RESET_SMB14 12 > > +#define NPCM8XX_RESET_SHA 13 > > +#define NPCM8XX_RESET_SEC_ECC 14 > > +#define NPCM8XX_RESET_PCIE_RC 15 > > +#define NPCM8XX_RESET_TIMER_10_14 16 > > +#define NPCM8XX_RESET_RNG 17 > > +#define NPCM8XX_RESET_SMB15 18 > > +#define NPCM8XX_RESET_SMB8 19 > > +#define NPCM8XX_RESET_SMB9 20 > > +#define NPCM8XX_RESET_SMB10 21 > > +#define NPCM8XX_RESET_SMB11 22 > > +#define NPCM8XX_RESET_ESPI 23 > > +#define NPCM8XX_RESET_USB_PHY_1 24 > > +#define NPCM8XX_RESET_USB_PHY_2 25 > > + > > > Best regards, > Krzysztof > Best regards, Tomer --00000000000047e8b705dfae4eb7 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi=C2=A0Krzysztof,
=

Thanks for your comments.
=


On Mon, 23 May 2022 at 12:01, Krzysztof Kozlowsk= i <krzysztof.kozlowski= @linaro.org> wrote:
On 22/05/2022 17:50, Tomer Maimon wrote:
> Add binding document and device tree binding
> constants for Nuvoton BMC NPCM8XX reset controller.
>
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>=C2=A0 .../bindings/reset/nuvoton,npcm-reset.txt=C2=A0 =C2=A0 =C2=A0|= =C2=A0 17 ++-
>=C2=A0 .../dt-bindings/reset/nuvoton,npcm8xx-reset.h | 124 ++++++++++++= ++++++
>=C2=A0 2 files changed, 139 insertions(+), 2 deletions(-)
>=C2=A0 create mode 100644 include/dt-bindings/reset/nuvoton,npcm8xx-res= et.h
>
> diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm-rese= t.txt b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> index cb1613092ee7..b7eb8615b68b 100644
> --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt > +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt > @@ -1,14 +1,15 @@
>=C2=A0 Nuvoton NPCM Reset controller
>=C2=A0
>=C2=A0 Required properties:
> -- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
> +- compatible : "nuvoton,npcm750-reset" for Poleg NPCM7XX BM= C.
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"nuvoton,= npcm845-reset" for Arbel NPCM8XX BMC.
>=C2=A0 - reg : specifies physical base address and size of the register= .
>=C2=A0 - #reset-cells: must be set to 2
>=C2=A0 - syscon: a phandle to access GCR registers.
>=C2=A0
>=C2=A0 Optional property:
>=C2=A0 - nuvoton,sw-reset-number - Contains the software reset number t= o restart the SoC.
> -=C2=A0 NPCM7xx contain four software reset that represent numbers 1 t= o 4.
> +=C2=A0 NPCM7xx and NPCM8xx contain four software reset that represent= numbers 1 to 4.
>=C2=A0
>=C2=A0 =C2=A0 If 'nuvoton,sw-reset-number' is not specified sof= tware reset is disabled.
>=C2=A0
> @@ -32,3 +33,15 @@ example:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 };
>=C2=A0
>=C2=A0 The index could be found in <dt-bindings/reset/nuvoton,npcm7x= x-reset.h>.
> +
> +Specifying reset lines connected to IP NPCM8XX modules
> +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D

we prefer=C2=A0to=C2=A0use the same explanation as th= e NPCM7XX reset explanation in the reset binding document.
No need to document consumers. Just mention the header.

> +example:
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 spi0: spi@..... {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ...
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 resets =3D &l= t;&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_PSPI1>;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ...
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 };
> +
> +The index could be found in <dt-bindings/reset/nuvoton,npcm8xx-res= et.h>.
> diff --git a/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h b/inclu= de/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> new file mode 100644
> index 000000000000..4b832a0fd1dd
> --- /dev/null
> +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h
> @@ -0,0 +1,124 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Dual license.
O.K.=C2=A0

> +// Copyright (c) 2022 Nuvoton Technology corporation.
> +
> +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H
> +#define _DT_BINDINGS_NPCM8XX_RESET_H
> +
> +#define NPCM8XX_RESET_IPSRST1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 0x20
> +#define NPCM8XX_RESET_IPSRST2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 0x24
> +#define NPCM8XX_RESET_IPSRST3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 0x34
> +#define NPCM8XX_RESET_IPSRST4=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 0x74

What are these? All IDs should be incremental, decimal and start from 0.
Register offset, we use the same method in NPCM7xx. plea= se refer


> +
> +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */
> +#define NPCM8XX_RESET_GDMA0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 3

IDs start from 0 and do not have holes.


> +#define NPCM8XX_RESET_UDC1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A05<= br> > +#define NPCM8XX_RESET_GMAC3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 6
> +#define NPCM8XX_RESET_UART_2_3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A07
> +#define NPCM8XX_RESET_UDC2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A08<= br> > +#define NPCM8XX_RESET_PECI=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A09<= br> > +#define NPCM8XX_RESET_AES=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 10=
> +#define NPCM8XX_RESET_UART_0_1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A011
> +#define NPCM8XX_RESET_MC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A012
> +#define NPCM8XX_RESET_SMB2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A013=
> +#define NPCM8XX_RESET_SMB3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A014=
> +#define NPCM8XX_RESET_SMB4=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A015=
> +#define NPCM8XX_RESET_SMB5=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A016=
> +#define NPCM8XX_RESET_PWM_M0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A018
> +#define NPCM8XX_RESET_TIMER_0_4=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 19
> +#define NPCM8XX_RESET_TIMER_5_9=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 20
> +#define NPCM8XX_RESET_GMAC4=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 21
> +#define NPCM8XX_RESET_UDC4=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A022=
> +#define NPCM8XX_RESET_UDC5=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A023=
> +#define NPCM8XX_RESET_UDC6=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A024=
> +#define NPCM8XX_RESET_UDC3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A025=
> +#define NPCM8XX_RESET_ADC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 27=
> +#define NPCM8XX_RESET_SMB6=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A028=
> +#define NPCM8XX_RESET_SMB7=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A029=
> +#define NPCM8XX_RESET_SMB0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A030=
> +#define NPCM8XX_RESET_SMB1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A031=
> +
> +/* Reset lines on IP2 reset module (NPCM8XX_RESET_IPSRST2) */
> +#define NPCM8XX_RESET_MFT0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00<= br> > +#define NPCM8XX_RESET_MFT1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A01<= br> > +#define NPCM8XX_RESET_MFT2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A02<= br> > +#define NPCM8XX_RESET_MFT3=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A03<= br> > +#define NPCM8XX_RESET_MFT4=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A04<= br> > +#define NPCM8XX_RESET_MFT5=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A05<= br> > +#define NPCM8XX_RESET_MFT6=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A06<= br> > +#define NPCM8XX_RESET_MFT7=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A07<= br> > +#define NPCM8XX_RESET_MMC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 8<= br> > +#define NPCM8XX_RESET_GFX_SYS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 10
> +#define NPCM8XX_RESET_AHB_PCIBRG=C2=A0 =C2=A0 =C2=A011
> +#define NPCM8XX_RESET_VDMA=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A012=
> +#define NPCM8XX_RESET_ECE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 13=
> +#define NPCM8XX_RESET_VCD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 14=
> +#define NPCM8XX_RESET_VIRUART1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A016
> +#define NPCM8XX_RESET_VIRUART2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A017
> +#define NPCM8XX_RESET_SIOX1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 18
> +#define NPCM8XX_RESET_SIOX2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 19
> +#define NPCM8XX_RESET_BT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A020
> +#define NPCM8XX_RESET_3DES=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A021=
> +#define NPCM8XX_RESET_PSPI2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 23
> +#define NPCM8XX_RESET_GMAC2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 25
> +#define NPCM8XX_RESET_USBH1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 26
> +#define NPCM8XX_RESET_GMAC1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 28
> +#define NPCM8XX_RESET_CP1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 31=
> +
> +/* Reset lines on IP3 reset module (NPCM8XX_RESET_IPSRST3) */
> +#define NPCM8XX_RESET_PWM_M1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00
> +#define NPCM8XX_RESET_SMB12=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 1
> +#define NPCM8XX_RESET_SPIX=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A02<= br> > +#define NPCM8XX_RESET_SMB13=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 3
> +#define NPCM8XX_RESET_UDC0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A04<= br> > +#define NPCM8XX_RESET_UDC7=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A05<= br> > +#define NPCM8XX_RESET_UDC8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A06<= br> > +#define NPCM8XX_RESET_UDC9=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A07<= br> > +#define NPCM8XX_RESET_USBHUB=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A08
> +#define NPCM8XX_RESET_PCI_MAILBOX=C2=A0 =C2=A0 9
> +#define NPCM8XX_RESET_GDMA1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 10
> +#define NPCM8XX_RESET_GDMA2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 11
> +#define NPCM8XX_RESET_SMB14=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 12
> +#define NPCM8XX_RESET_SHA=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 13=
> +#define NPCM8XX_RESET_SEC_ECC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 14
> +#define NPCM8XX_RESET_PCIE_RC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 15
> +#define NPCM8XX_RESET_TIMER_10_14=C2=A0 =C2=A0 16
> +#define NPCM8XX_RESET_RNG=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 17=
> +#define NPCM8XX_RESET_SMB15=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 18
> +#define NPCM8XX_RESET_SMB8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A019=
> +#define NPCM8XX_RESET_SMB9=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A020=
> +#define NPCM8XX_RESET_SMB10=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 21
> +#define NPCM8XX_RESET_SMB11=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 22
> +#define NPCM8XX_RESET_ESPI=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A023=
> +#define NPCM8XX_RESET_USB_PHY_1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 24
> +#define NPCM8XX_RESET_USB_PHY_2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 25
> +


Best regards,
Krzysztof

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