From: Paul Gortmaker <paul.gortmaker@windriver.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] MPC8313 DDR2 configuration
Date: Tue, 7 Feb 2012 23:45:31 -0500 [thread overview]
Message-ID: <CAP=VYLpZVCKYFp7C6TELsST+JYMkNC+n1vfQjB=Fotz9V6UDcA@mail.gmail.com> (raw)
In-Reply-To: <001d01cce5b8$d5a5ae50$80f10af0$@a2etech.com>
On Tue, Feb 7, 2012 at 11:52 AM, Scott Larson <slarson@a2etech.com> wrote:
> Hi,
>
> Looking for help on DDR2 configuration in u-boot.
>
>
>
> I have the MPC8313ERDB from Freescale. It has 128Mbytes of DDR2 ram. The
> existing 128MByte that uses only CS0.
>
>
>
> I have a new board design to bring up.
>
> The timing parameters are all ok but I need some guidance on changing the
> settings to suit my memory configuration.
>
>
>
> My board has 512Mbytes on CS0 and 512Mbytes on CS1.
>
> Changes need to be made to files MPC8313ERDB.h and sdram.c
SODIMM with SPD? Autoconfig with CONFIG_SPD_EEPROM is
nice compared to hard coding values, if you can use it. I'm pretty
sure it works fine on sbc8349 board.
>
>
>
> I have made all the row and column size and block address pin settings ok. I
> have set DDR size to 512Mbytes (per Chip Select).
>
>
>
> I need some guidance on the setting for CS1 bank of ram.
Have you created the CONFIG_SYS_BR1_PRELIM and the
CONFIG_SYS_OR1_PRELIM defines in your board header?
If you copied these from a reference platform, they may still
be populated with settings appropriate for flash up at the top
of memory instead of DDR2 settings for your 2nd bank...
P.
>
>
>
> thanks
>
> Scott
>
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
next prev parent reply other threads:[~2012-02-08 4:45 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-02-07 16:52 [U-Boot] MPC8313 DDR2 configuration Scott Larson
2012-02-08 4:45 ` Paul Gortmaker [this message]
2012-02-08 10:15 ` Scott Larson
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