From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C6C8C2D0DB for ; Mon, 20 Jan 2020 12:57:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CD61320678 for ; Mon, 20 Jan 2020 12:57:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="oIvn2DaF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728249AbgATM5R (ORCPT ); Mon, 20 Jan 2020 07:57:17 -0500 Received: from mail-vk1-f195.google.com ([209.85.221.195]:38048 "EHLO mail-vk1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728205AbgATM5R (ORCPT ); Mon, 20 Jan 2020 07:57:17 -0500 Received: by mail-vk1-f195.google.com with SMTP id d17so8499217vke.5 for ; Mon, 20 Jan 2020 04:57:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Erqm0aFOSa6psKmkMM6lnX3PdtaHFG7CqC73/ShnOgE=; b=oIvn2DaFOmDBRMU/LWWYMrlPpxBIyNalp5DZiF+C3uwh9Ku1Amip7DyNmcGok5hS2w RZfAk8F38RPTFw6DbdF8a6iylQK47J2jnPW+SP8tzP3nF0dLQtLAJLwKA3kFolXRPxrL z5y385aq1bSYG0R7iWMQv5OfVsyoFmdxrxaBMBb9Ry0F9PyUBFiF5cAU3WYFBLBy5K4C krpPkU9xkgoM5cEHyXzlE0JNxz9qKKsgGZlsjodImwaQMUgRLx5w2UiXgLS641LrXYgT sOHOajLGsC9kGXgNFyFxhBPOXpiVSdcVAM0UH0OcUcWZ4UBJOIhRw28gjWUtQz5coi8J 8Xhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Erqm0aFOSa6psKmkMM6lnX3PdtaHFG7CqC73/ShnOgE=; b=jAXoZZ9i8ij5EfBWJ1+7bUzIv5NSprVttjpU1hHJtfLmkvqSa5AWA1dKRAZshu9FEa Lk6Ch/6pvm8rI309+xwjBe3cQ+cf3ken30oJZDnsDIz5nNaGkH8ezYzMolNBjVWjvpq0 QJH2CZ4sZIgoxNstEl6jSb1OI0UW6EvsuDw7uz7FB6hfQcUONv/s5B6r588JX3dJPg6h KO5a4T+4JY+wG7X2iTmR1wujuQqk/d8ed7G8U551c4LeG+NmLCC3DqFww0PEDTvH2ZRF o5xT5keB+iLJqIAAjEvNIiqCf7DXnqHv4H5TMhAIwOVpmxz/SdmcyI9Q1SHihL8rmPuh gjFg== X-Gm-Message-State: APjAAAWneI3yHRSDmtMR6x5cLKv2P2fsVzbomv0EszT1cwkHeOGipddi 0mpdP2JouIRz5hsg6qiDYxx9ColPs+5oBVuwT8az1w== X-Google-Smtp-Source: APXvYqzl429VNKmi90BhlVMLUv70+Dvovd6UjSP+sNzyPodBHttqWUX8SVBodhNRSQgG/UGM/kw+amRqAPDxjqXy58g= X-Received: by 2002:a1f:4541:: with SMTP id s62mr763808vka.59.1579525035558; Mon, 20 Jan 2020 04:57:15 -0800 (PST) MIME-Version: 1.0 References: <20191230144402.30195-1-ulf.hansson@linaro.org> <20191230144402.30195-3-ulf.hansson@linaro.org> In-Reply-To: From: Ulf Hansson Date: Mon, 20 Jan 2020 13:56:39 +0100 Message-ID: Subject: Re: [PATCH v5 02/15] dt: psci: Update DT bindings to support hierarchical PSCI states To: Rob Herring Cc: Sudeep Holla , Lorenzo Pieralisi , "open list:THERMAL" , "Rafael J . Wysocki" , Daniel Lezcano , Mark Rutland , Lina Iyer , Vincent Guittot , Stephen Boyd , Andy Gross , Bjorn Andersson , Kevin Hilman , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , linux-arm-msm , Lina Iyer Content-Type: text/plain; charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri, 17 Jan 2020 at 18:36, Rob Herring wrote: > > On Fri, Jan 17, 2020 at 10:42 AM Ulf Hansson wrote: > > > > On Thu, 16 Jan 2020 at 19:19, Rob Herring wrote: > > > > > > On Tue, Jan 14, 2020 at 11:55 AM Ulf Hansson wrote: > > > > > > > > On Mon, 13 Jan 2020 at 20:53, Rob Herring wrote: > > > > > > > > > > On Mon, Dec 30, 2019 at 8:44 AM Ulf Hansson wrote: > > > > > > > > > > > > Update PSCI DT bindings to allow to represent idle states for CPUs and the > > > > > > CPU topology, by using a hierarchical layout. Primarily this is done by > > > > > > re-using the existing DT bindings for PM domains [1] and for PM domain idle > > > > > > states [2]. > > > > > > > > > > > > Let's also add an example into the document for the PSCI DT bindings, to > > > > > > clearly show the new hierarchical based layout. The currently supported > > > > > > flattened layout, is already described in the ARM idle states bindings [3], > > > > > > so let's leave that as is. > > > > > > > > > > > > [1] Documentation/devicetree/bindings/power/power_domain.txt > > > > > > [2] Documentation/devicetree/bindings/power/domain-idle-state.txt > > > > > > [3] Documentation/devicetree/bindings/arm/idle-states.txt > > > > > > > > > > > > Co-developed-by: Lina Iyer > > > > > > Signed-off-by: Lina Iyer > > > > > > Reviewed-by: Sudeep Holla > > > > > > Signed-off-by: Ulf Hansson > > > > > > --- > > > > > > > > > > > > Changes in v5: > > > > > > - None. > > > > > > > > > > First I'm seeing this as the DT list was not copied. The example has > > > > > problems when running 'make dt_binding_check': > > > > > > > > > > Documentation/devicetree/bindings/arm/psci.example.dt.yaml: cpu@0: > > > > > compatible: Additional items are not allowed ('arm,armv8' was > > > > > unexpected) > > > > > Documentation/devicetree/bindings/arm/psci.example.dt.yaml: cpu@0: > > > > > compatible: ['arm,cortex-a53', 'arm,armv8'] is too long > > > > > Documentation/devicetree/bindings/arm/psci.example.dt.yaml: cpu@1: > > > > > compatible: Additional items are not allowed ('arm,armv8' was > > > > > unexpected) > > > > > Documentation/devicetree/bindings/arm/psci.example.dt.yaml: cpu@1: > > > > > compatible: ['arm,cortex-a57', 'arm,armv8'] is too long > > > > > > > > > > 'arm,armv8' is only valid for s/w models. > > > > > > > > Perhaps you have a different version of the tools than I have (I have > > > > tried both on v.5.5-rc5 and todays linux-next), because I can't > > > > reproduce these errors at my side when running "make > > > > dt_binding_check". > > > > > > > > Can you please check again? > > > > > > Are you setting DT_SCHEMA_FILES? If so, then arm/cpus.yaml (or any > > > other schema) isn't loaded and used for validation. That schema is the > > > source of this error. > > > > Yes. Aha, that's why then. Perhaps that needs to be clarified > > somewhere in the documentation of tool. > > Patches welcome. :) I'm kind of tired of writing documentation that no > one comments on and and seemingly only sometimes read. :( I understand your concerns. A patch is on it's way. > > > Anyway, I used because it was kind of hard to process all the error > > output one gets when building all yaml files at once. > > dtbs_check has a lot which is where setting DT_SCHEMA_FILES is > primarily useful. dt_binding_check should be error/warning free, but > yes linux-next and rc1/2 are frequently broken. > > > > It is failing in my CI job: > > > https://gitlab.com/robherring/linux-dt-bindings/-/jobs/405298185 > > > > > > Is dt-schema up to date? Though I can't think of any recent changes > > > that would impact this. This check has been there a while and I fixed > > > all the dts files. > > > > > > Do you see psci.example.dt.yaml getting built? > > > > Yes, but with using DT_SCHEMA_FILES. > > > > Anyway, now I can re-produced the errors, so then I should be able to > > fix them. :-) > > > > > > > > > > Documentation/devicetree/bindings/arm/psci.example.dt.yaml: > > > > > idle-states: cluster-retention:compatible:0: 'arm,idle-state' was > > > > > expected > > > > > Documentation/devicetree/bindings/arm/psci.example.dt.yaml: > > > > > idle-states: cluster-power-down:compatible:0: 'arm,idle-state' was > > > > > expected > > > > > > > > > > The last 2 are due to my conversion of the idle-states binding which > > > > > is in my tree now. Probably need to add 'domain-idle-state' as a > > > > > compatible at a minimum. It looks like domain-idle-state.txt is pretty > > > > > much the same as arm/idle-state.txt, so we should perhaps merge them. > > > > > > > > Ahh, so maybe *all* of the above problems are caused by conflicts in > > > > the arm-soc tree with changes from your tree!? > > > > > > Shouldn't be. arm/cpus.yaml has been in place for a few cycles now. > > > > > > > > > > > In regards to merging files, I am fine by that if that helps. > > > > > > > > > > > > > > There's some bigger issues though. > > > > > > > > > > > --- > > > > > > .../devicetree/bindings/arm/cpus.yaml | 15 +++ > > > > > > .../devicetree/bindings/arm/psci.yaml | 104 ++++++++++++++++++ > > > > > > 2 files changed, 119 insertions(+) > > > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml > > > > > > index c23c24ff7575..7a9c3ce2dbef 100644 > > > > > > --- a/Documentation/devicetree/bindings/arm/cpus.yaml > > > > > > +++ b/Documentation/devicetree/bindings/arm/cpus.yaml > > > > > > @@ -242,6 +242,21 @@ properties: > > > > > > > > > > > > where voltage is in V, frequency is in MHz. > > > > > > > > > > > > + power-domains: > > > > > > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > > > > > > + description: > > > > > > + List of phandles and PM domain specifiers, as defined by bindings of the > > > > > > + PM domain provider (see also ../power_domain.txt). > > > > > > + > > > > > > + power-domain-names: > > > > > > + $ref: '/schemas/types.yaml#/definitions/string-array' > > > > > > + description: > > > > > > + A list of power domain name strings sorted in the same order as the > > > > > > + power-domains property. > > > > > > + > > > > > > + For PSCI based platforms, the name corresponding to the index of the PSCI > > > > > > + PM domain provider, must be "psci". > > > > > > + > > > > > > qcom,saw: > > > > > > $ref: '/schemas/types.yaml#/definitions/phandle' > > > > > > description: | > > > > > > diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml > > > > > > index 7abdf58b335e..8ef85420b2ab 100644 > > > > > > --- a/Documentation/devicetree/bindings/arm/psci.yaml > > > > > > +++ b/Documentation/devicetree/bindings/arm/psci.yaml > > > > > > @@ -102,6 +102,34 @@ properties: > > > > > > [1] Kernel documentation - ARM idle states bindings > > > > > > Documentation/devicetree/bindings/arm/idle-states.txt > > > > > > > > > > > > + "#power-domain-cells": > > > > > > > > > > This is wrong because you are saying the /psci node should have these > > > > > properties. You need to define the child nodes (at least a pattern you > > > > > can match on) and put these properties there. > > > > > > > > Right, good point. > > > > > > > > I searched for some similar examples for how to encode this, but > > > > couldn't really find something useful. > > > > > > You need something like: > > > > > > patternProperties: > > > '^(cluster|cpu)-pd[0-9a-f]+$': > > > type: object > > > properties: > > > ... and then the properties in the child nodes > > > > > > Note that its going to look weird for the 10th PD with 'cpu-pda'. So > > > maybe add a '-'. > > > > > > > Great, I try this! Thanks. > > > > > > One more thing, it seems like > > > > this change is also needed for the common power-domain bindings, as > > > > that also specifies parent/childs domains. > > > > > > Normally, we'd have a $ref to power-domain.yaml, but for that to work > > > here, you'll have to expand the node names ($nodename). > > > > Not sure I get that, but interpret this as it's not a good idea to use > > a $ref to power-domain.yaml. Right? > > It means either this binding is odd or power-domain.yaml needs some > more work or both. Ideally, we only have 1 type definition of any > property name. > > Probably the easiest thing to do is extend the node name pattern to > something like this: > > pattern: "^(power-controller|power-domain)([@\-].*)?$" > > And then name your nodes like this: > > power-domain-cpu-0 > power-domain-cluster > > That's more consistent anyways. Looks like a good idea! I try that. > > > > > Anyway, I would really appreciate if you can suggest something more > > > > detailed for you think this should be done!? > > > > > > > > > > > > > > > + description: > > > > > > + The number of cells in a PM domain specifier as per binding in [3]. > > > > > > + Must be 0 as to represent a single PM domain. > > > > > > + > > > > > > + ARM systems can have multiple cores, sometimes in an hierarchical > > > > > > + arrangement. This often, but not always, maps directly to the processor > > > > > > + power topology of the system. Individual nodes in a topology have their > > > > > > + own specific power states and can be better represented hierarchically. > > > > > > + > > > > > > + For these cases, the definitions of the idle states for the CPUs and the > > > > > > + CPU topology, must conform to the binding in [3]. The idle states > > > > > > + themselves must conform to the binding in [4] and must specify the > > > > > > + arm,psci-suspend-param property. > > > > > > + > > > > > > + It should also be noted that, in PSCI firmware v1.0 the OS-Initiated > > > > > > + (OSI) CPU suspend mode is introduced. Using a hierarchical representation > > > > > > + helps to implement support for OSI mode and OS implementations may choose > > > > > > + to mandate it. > > > > > > + > > > > > > + [3] Documentation/devicetree/bindings/power/power_domain.txt > > > > > > + [4] Documentation/devicetree/bindings/power/domain-idle-state.txt > > > > > > + > > > > > > + power-domains: > > > > > > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > > > > > > + description: > > > > > > + List of phandles and PM domain specifiers, as defined by bindings of the > > > > > > + PM domain provider. > > > > > > > > > > A schema for 'domain-idle-states' property is missing. > > > > > > > > Right, let's figure out the best way for how to add that. > > > > > > If power-domain.yaml is referenced, then don't need anything else > > > unless you can define the number of phandles (looks like you can't?). > > > > The number phandles should be one. At least, I think we can start with > > that and extend the binding if needed. > > But there's 2 for the cluster in the example. What example do you refer to? For each power controller node for psci, only one phandle needs to be specified in "power-domains", as that should be sufficient to describe the topology. When it comes to the CPU node, multiple phandles may need to specified in "power-domains". > > > How would that look like then? Apologize for my ignorance (I really > > need to spend some time learning this better)... > > Basically, anything common that can be an multiple entries is defined as: > > power-domains: > maxItems: 1 > > if only 1 entry or for multiple you need to define each entry: > > power-domains: > items: > - description: what the first power domain is > - description: what the 2nd power domain is Okay. This should be fine for the PSCI power controller node, but for the generic binding in cpus.yaml I am not sure how to describe this as that would be SoC specific. The number of phandles in power-domains could differ between SoCs at CPU node. However, at most, one would be a phandle for PSCI. If additional those would be for something different. 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Wysocki" , Lina Iyer , Bjorn Andersson , Kevin Hilman , Andy Gross , Lina Iyer , Sudeep Holla , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 17 Jan 2020 at 18:36, Rob Herring wrote: > > On Fri, Jan 17, 2020 at 10:42 AM Ulf Hansson wrote: > > > > On Thu, 16 Jan 2020 at 19:19, Rob Herring wrote: > > > > > > On Tue, Jan 14, 2020 at 11:55 AM Ulf Hansson wrote: > > > > > > > > On Mon, 13 Jan 2020 at 20:53, Rob Herring wrote: > > > > > > > > > > On Mon, Dec 30, 2019 at 8:44 AM Ulf Hansson wrote: > > > > > > > > > > > > Update PSCI DT bindings to allow to represent idle states for CPUs and the > > > > > > CPU topology, by using a hierarchical layout. Primarily this is done by > > > > > > re-using the existing DT bindings for PM domains [1] and for PM domain idle > > > > > > states [2]. > > > > > > > > > > > > Let's also add an example into the document for the PSCI DT bindings, to > > > > > > clearly show the new hierarchical based layout. The currently supported > > > > > > flattened layout, is already described in the ARM idle states bindings [3], > > > > > > so let's leave that as is. > > > > > > > > > > > > [1] Documentation/devicetree/bindings/power/power_domain.txt > > > > > > [2] Documentation/devicetree/bindings/power/domain-idle-state.txt > > > > > > [3] Documentation/devicetree/bindings/arm/idle-states.txt > > > > > > > > > > > > Co-developed-by: Lina Iyer > > > > > > Signed-off-by: Lina Iyer > > > > > > Reviewed-by: Sudeep Holla > > > > > > Signed-off-by: Ulf Hansson > > > > > > --- > > > > > > > > > > > > Changes in v5: > > > > > > - None. > > > > > > > > > > First I'm seeing this as the DT list was not copied. The example has > > > > > problems when running 'make dt_binding_check': > > > > > > > > > > Documentation/devicetree/bindings/arm/psci.example.dt.yaml: cpu@0: > > > > > compatible: Additional items are not allowed ('arm,armv8' was > > > > > unexpected) > > > > > Documentation/devicetree/bindings/arm/psci.example.dt.yaml: cpu@0: > > > > > compatible: ['arm,cortex-a53', 'arm,armv8'] is too long > > > > > Documentation/devicetree/bindings/arm/psci.example.dt.yaml: cpu@1: > > > > > compatible: Additional items are not allowed ('arm,armv8' was > > > > > unexpected) > > > > > Documentation/devicetree/bindings/arm/psci.example.dt.yaml: cpu@1: > > > > > compatible: ['arm,cortex-a57', 'arm,armv8'] is too long > > > > > > > > > > 'arm,armv8' is only valid for s/w models. > > > > > > > > Perhaps you have a different version of the tools than I have (I have > > > > tried both on v.5.5-rc5 and todays linux-next), because I can't > > > > reproduce these errors at my side when running "make > > > > dt_binding_check". > > > > > > > > Can you please check again? > > > > > > Are you setting DT_SCHEMA_FILES? If so, then arm/cpus.yaml (or any > > > other schema) isn't loaded and used for validation. That schema is the > > > source of this error. > > > > Yes. Aha, that's why then. Perhaps that needs to be clarified > > somewhere in the documentation of tool. > > Patches welcome. :) I'm kind of tired of writing documentation that no > one comments on and and seemingly only sometimes read. :( I understand your concerns. A patch is on it's way. > > > Anyway, I used because it was kind of hard to process all the error > > output one gets when building all yaml files at once. > > dtbs_check has a lot which is where setting DT_SCHEMA_FILES is > primarily useful. dt_binding_check should be error/warning free, but > yes linux-next and rc1/2 are frequently broken. > > > > It is failing in my CI job: > > > https://gitlab.com/robherring/linux-dt-bindings/-/jobs/405298185 > > > > > > Is dt-schema up to date? Though I can't think of any recent changes > > > that would impact this. This check has been there a while and I fixed > > > all the dts files. > > > > > > Do you see psci.example.dt.yaml getting built? > > > > Yes, but with using DT_SCHEMA_FILES. > > > > Anyway, now I can re-produced the errors, so then I should be able to > > fix them. :-) > > > > > > > > > > Documentation/devicetree/bindings/arm/psci.example.dt.yaml: > > > > > idle-states: cluster-retention:compatible:0: 'arm,idle-state' was > > > > > expected > > > > > Documentation/devicetree/bindings/arm/psci.example.dt.yaml: > > > > > idle-states: cluster-power-down:compatible:0: 'arm,idle-state' was > > > > > expected > > > > > > > > > > The last 2 are due to my conversion of the idle-states binding which > > > > > is in my tree now. Probably need to add 'domain-idle-state' as a > > > > > compatible at a minimum. It looks like domain-idle-state.txt is pretty > > > > > much the same as arm/idle-state.txt, so we should perhaps merge them. > > > > > > > > Ahh, so maybe *all* of the above problems are caused by conflicts in > > > > the arm-soc tree with changes from your tree!? > > > > > > Shouldn't be. arm/cpus.yaml has been in place for a few cycles now. > > > > > > > > > > > In regards to merging files, I am fine by that if that helps. > > > > > > > > > > > > > > There's some bigger issues though. > > > > > > > > > > > --- > > > > > > .../devicetree/bindings/arm/cpus.yaml | 15 +++ > > > > > > .../devicetree/bindings/arm/psci.yaml | 104 ++++++++++++++++++ > > > > > > 2 files changed, 119 insertions(+) > > > > > > > > > > > > diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml > > > > > > index c23c24ff7575..7a9c3ce2dbef 100644 > > > > > > --- a/Documentation/devicetree/bindings/arm/cpus.yaml > > > > > > +++ b/Documentation/devicetree/bindings/arm/cpus.yaml > > > > > > @@ -242,6 +242,21 @@ properties: > > > > > > > > > > > > where voltage is in V, frequency is in MHz. > > > > > > > > > > > > + power-domains: > > > > > > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > > > > > > + description: > > > > > > + List of phandles and PM domain specifiers, as defined by bindings of the > > > > > > + PM domain provider (see also ../power_domain.txt). > > > > > > + > > > > > > + power-domain-names: > > > > > > + $ref: '/schemas/types.yaml#/definitions/string-array' > > > > > > + description: > > > > > > + A list of power domain name strings sorted in the same order as the > > > > > > + power-domains property. > > > > > > + > > > > > > + For PSCI based platforms, the name corresponding to the index of the PSCI > > > > > > + PM domain provider, must be "psci". > > > > > > + > > > > > > qcom,saw: > > > > > > $ref: '/schemas/types.yaml#/definitions/phandle' > > > > > > description: | > > > > > > diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml > > > > > > index 7abdf58b335e..8ef85420b2ab 100644 > > > > > > --- a/Documentation/devicetree/bindings/arm/psci.yaml > > > > > > +++ b/Documentation/devicetree/bindings/arm/psci.yaml > > > > > > @@ -102,6 +102,34 @@ properties: > > > > > > [1] Kernel documentation - ARM idle states bindings > > > > > > Documentation/devicetree/bindings/arm/idle-states.txt > > > > > > > > > > > > + "#power-domain-cells": > > > > > > > > > > This is wrong because you are saying the /psci node should have these > > > > > properties. You need to define the child nodes (at least a pattern you > > > > > can match on) and put these properties there. > > > > > > > > Right, good point. > > > > > > > > I searched for some similar examples for how to encode this, but > > > > couldn't really find something useful. > > > > > > You need something like: > > > > > > patternProperties: > > > '^(cluster|cpu)-pd[0-9a-f]+$': > > > type: object > > > properties: > > > ... and then the properties in the child nodes > > > > > > Note that its going to look weird for the 10th PD with 'cpu-pda'. So > > > maybe add a '-'. > > > > > > > Great, I try this! Thanks. > > > > > > One more thing, it seems like > > > > this change is also needed for the common power-domain bindings, as > > > > that also specifies parent/childs domains. > > > > > > Normally, we'd have a $ref to power-domain.yaml, but for that to work > > > here, you'll have to expand the node names ($nodename). > > > > Not sure I get that, but interpret this as it's not a good idea to use > > a $ref to power-domain.yaml. Right? > > It means either this binding is odd or power-domain.yaml needs some > more work or both. Ideally, we only have 1 type definition of any > property name. > > Probably the easiest thing to do is extend the node name pattern to > something like this: > > pattern: "^(power-controller|power-domain)([@\-].*)?$" > > And then name your nodes like this: > > power-domain-cpu-0 > power-domain-cluster > > That's more consistent anyways. Looks like a good idea! I try that. > > > > > Anyway, I would really appreciate if you can suggest something more > > > > detailed for you think this should be done!? > > > > > > > > > > > > > > > + description: > > > > > > + The number of cells in a PM domain specifier as per binding in [3]. > > > > > > + Must be 0 as to represent a single PM domain. > > > > > > + > > > > > > + ARM systems can have multiple cores, sometimes in an hierarchical > > > > > > + arrangement. This often, but not always, maps directly to the processor > > > > > > + power topology of the system. Individual nodes in a topology have their > > > > > > + own specific power states and can be better represented hierarchically. > > > > > > + > > > > > > + For these cases, the definitions of the idle states for the CPUs and the > > > > > > + CPU topology, must conform to the binding in [3]. The idle states > > > > > > + themselves must conform to the binding in [4] and must specify the > > > > > > + arm,psci-suspend-param property. > > > > > > + > > > > > > + It should also be noted that, in PSCI firmware v1.0 the OS-Initiated > > > > > > + (OSI) CPU suspend mode is introduced. Using a hierarchical representation > > > > > > + helps to implement support for OSI mode and OS implementations may choose > > > > > > + to mandate it. > > > > > > + > > > > > > + [3] Documentation/devicetree/bindings/power/power_domain.txt > > > > > > + [4] Documentation/devicetree/bindings/power/domain-idle-state.txt > > > > > > + > > > > > > + power-domains: > > > > > > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > > > > > > + description: > > > > > > + List of phandles and PM domain specifiers, as defined by bindings of the > > > > > > + PM domain provider. > > > > > > > > > > A schema for 'domain-idle-states' property is missing. > > > > > > > > Right, let's figure out the best way for how to add that. > > > > > > If power-domain.yaml is referenced, then don't need anything else > > > unless you can define the number of phandles (looks like you can't?). > > > > The number phandles should be one. At least, I think we can start with > > that and extend the binding if needed. > > But there's 2 for the cluster in the example. What example do you refer to? For each power controller node for psci, only one phandle needs to be specified in "power-domains", as that should be sufficient to describe the topology. When it comes to the CPU node, multiple phandles may need to specified in "power-domains". > > > How would that look like then? Apologize for my ignorance (I really > > need to spend some time learning this better)... > > Basically, anything common that can be an multiple entries is defined as: > > power-domains: > maxItems: 1 > > if only 1 entry or for multiple you need to define each entry: > > power-domains: > items: > - description: what the first power domain is > - description: what the 2nd power domain is Okay. This should be fine for the PSCI power controller node, but for the generic binding in cpus.yaml I am not sure how to describe this as that would be SoC specific. The number of phandles in power-domains could differ between SoCs at CPU node. However, at most, one would be a phandle for PSCI. If additional those would be for something different. Kind regards Uffe _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel