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bh=hZlTrXOnOwfkVp4IP+6nAkc4tSWReJL+ojzi0R++f14=; b=GEMDJwo4eLFtJpBqQkd1Zp7vzvUp1peNV7iNDGAMdlWTLZFXOTUOdW5y8dcaOGcjcc ghqw5E4vXAdpDCY3of1a03ucpwjOQb2qVwAm32A5NqbsvBrx1KQLFUHevpE1XXkFH9gC ++oSIUbb9fI0CBOMn69AdKkImHx7PxXjD8mL6HetGjdV06AGfwswZc9oWLsBCqEBbZbS E9lskOxI1Y3XRzvNFWXIRjTQ/o7j5BB9O2EfSyRBDyPHbHVUUhhTWin+oS8R0pnEGKmg gszgeSw6zpiGE7JSYjDVMrJgzgEWUyU4IuxA7XJGfQZfsQ+jzmO9RSlNX+p1Oih2hCq3 RrhQ== X-Gm-Message-State: AOAM530pGRDy8TIrNkBM5AbwSrj9rkD9exdNTT/ZxRpwyFrygOx8Q+8h Qvmk8OOh3WjeytHvh70gD8D5J2M0LrELJh5hIvX9JQ== X-Google-Smtp-Source: ABdhPJx5nD6+VY6q0OnqOl5s6XOx0kkRXFk6bupUgXJA2Srnp0YddIeGztSISa7PYxcs9vXwz90f3elk1mnLlhqIrg0= X-Received: by 2002:a1f:a68d:: with SMTP id p135mr4384673vke.6.1615461411571; Thu, 11 Mar 2021 03:16:51 -0800 (PST) MIME-Version: 1.0 References: <20210309015750.6283-1-peng.zhou@mediatek.com> In-Reply-To: <20210309015750.6283-1-peng.zhou@mediatek.com> From: Ulf Hansson Date: Thu, 11 Mar 2021 12:16:15 +0100 Message-ID: Subject: Re: [PATCH v2 2/4] mmc: Mediatek: enable crypto hardware engine To: Peng Zhou Cc: Eric Biggers , Chaotian Jing , "linux-mmc@vger.kernel.org" , DTML , Adrian Hunter , Satya Tangirala , Wulin Li Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, 9 Mar 2021 at 03:05, Peng Zhou wrote: > > Use SMC call enable hardware crypto engine > due to it only be changed in ATF(EL3). > > Signed-off-by: Peng Zhou > --- > drivers/mmc/host/mtk-sd.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > index 1c90360d6cf2..225ef5519161 100644 > --- a/drivers/mmc/host/mtk-sd.c > +++ b/drivers/mmc/host/mtk-sd.c > @@ -4,6 +4,7 @@ > * Author: Chaotian.Jing > */ > > +#include > #include > #include > #include > @@ -20,6 +21,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -319,6 +321,12 @@ > #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ > > #define PAD_DELAY_MAX 32 /* PAD delay cells */ > + > +/*--------------------------------------------------------------------------*/ > +/* SiP commands which used for crypto */ > +/*--------------------------------------------------------------------------*/ > +#define MTK_SIP_MMC_CONTROL MTK_SIP_SMC_CMD(0x273) > + > /*--------------------------------------------------------------------------*/ > /* Descriptor Structure */ > /*--------------------------------------------------------------------------*/ > @@ -2467,6 +2475,7 @@ static int msdc_of_clock_parse(struct platform_device *pdev, > > static int msdc_drv_probe(struct platform_device *pdev) > { > + struct arm_smccc_res smccc_res; > struct mmc_host *mmc; > struct msdc_host *host; > struct resource *res; > @@ -2616,6 +2625,15 @@ static int msdc_drv_probe(struct platform_device *pdev) > mmc->max_seg_size = 64 * 1024; > } > > + /* > + * 1: MSDC_AES_CTL_INIT > + * 4: cap_id, no-meaning now > + * 1: cfg_id, we choose the second cfg group > + */ > + if (mmc->caps2 & MMC_CAP2_CRYPTO) > + arm_smccc_smc(MTK_SIP_MMC_CONTROL, > + 1, 4, 1, 0, 0, 0, 0, &smccc_res); > + No, I don't want generic arm_smccc_smc calls in generic drivers like this. Moreover, shouldn't we "probe" the firmware to find out if this is supported and ready to be used? Perhaps something along the lines of what Qcom does in drivers/mmc/host/sdhci-msm.c and drivers/firmware/qcom_scm.c? > host->timeout_clks = 3 * 1048576; > host->dma.gpd = dma_alloc_coherent(&pdev->dev, > 2 * sizeof(struct mt_gpdma_desc), > @@ -2770,9 +2788,18 @@ static int __maybe_unused msdc_runtime_resume(struct device *dev) > { > struct mmc_host *mmc = dev_get_drvdata(dev); > struct msdc_host *host = mmc_priv(mmc); > + struct arm_smccc_res smccc_res; > > msdc_ungate_clock(host); > msdc_restore_reg(host); > + /* > + * 1: MSDC_AES_CTL_INIT > + * 4: cap_id, no-meaning now > + * 1: cfg_id, we choose the second cfg group > + */ > + if (mmc->caps2 & MMC_CAP2_CRYPTO) > + arm_smccc_smc(MTK_SIP_MMC_CONTROL, > + 1, 4, 1, 0, 0, 0, 0, &smccc_res); Ditto. > return 0; > } > Kind regards Uffe