From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 640B7CA9EA0 for ; Fri, 25 Oct 2019 14:13:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3844120663 for ; Fri, 25 Oct 2019 14:13:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bYS+y1MX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390715AbfJYONn (ORCPT ); Fri, 25 Oct 2019 10:13:43 -0400 Received: from mail-vs1-f67.google.com ([209.85.217.67]:38194 "EHLO mail-vs1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727367AbfJYONm (ORCPT ); Fri, 25 Oct 2019 10:13:42 -0400 Received: by mail-vs1-f67.google.com with SMTP id b123so1541735vsb.5 for ; Fri, 25 Oct 2019 07:13:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=uN8HSzjVWYgOa/f9HwJLZghBIB5LPa4au9Qp6QOM0oM=; b=bYS+y1MXgMPSuAWl/Pw+O36xYjUIvDi9LmeppA4i16Ap9cInMC5v97zMSThnwOwkjG G2R98nKwmRhuQLaCxO9vrs2HbOTFJZHZpG7DrkUY3bH1pCHq/QbLn8lTKAwuLAgCKShc 4ivCigJgcaIc1cTw4U/fd2FuRFK4kkU/nc6vWFttfGBxZtbBCdROsKcqDLrzGKbpvrUs 77BYTPAlKpSIq/S808KRqib4oAz/cBtdSKIcr7wgp8/wJsiyzd1lZzk80W3RkhDiLuxF LFZwMV9dUXwKr9wD+9Im/C7HqsbimiepPkPgw5VR/iu5I87i7i4eo83eDqHqOUSvCQPR 5bYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=uN8HSzjVWYgOa/f9HwJLZghBIB5LPa4au9Qp6QOM0oM=; b=oK2iOWx1NQaopHQEXT2BJvxe2VhL/XaWp7mePQEiixSoSYmG9au42E1X2leMjt8BKz p8F7tJhG1I3wUUXOQfCZcTHb1dNSlSC7owI1+IzzmQkafc+YEXmVs0g0nsukkxJs+nJ5 tYEUYjOM5g23DfiKt3jsnunNNgqZHYO2v0cbK86WQOUz4ewwzyb1H68RbwwqQak3XMrI 6rPJEJJhN2nDODRBJ9cy3VQVcPv87WaESkw6PEWreNmLBmlzTlOamfa954S1Prg9oZ7I hQzu5B03QWljF/PmkfYez+UmhThfCvB+DqVpBSqY15ur0gjgpTEdg5hCvEhpByYaj24D 37fw== X-Gm-Message-State: APjAAAV1Z6AQggWnkLIobUpRzKAZviYPtLUmHnvmQnVdEaVT7scEuk11 Q4APseHpWpCkYLBVR1c9elbv6g170sunUOOmILKBEA== X-Google-Smtp-Source: APXvYqwYv7TgejqODhekRI9dDIIRnGtrb3/+jOe+VBk6FoXTRU0DV374nPjN0wfCLfVDZUOhMqwIhHhSA35PTnmR0zY= X-Received: by 2002:a67:7ac5:: with SMTP id v188mr2030243vsc.191.1572012821656; Fri, 25 Oct 2019 07:13:41 -0700 (PDT) MIME-Version: 1.0 References: <20191010113937.15962-1-ulf.hansson@linaro.org> <20191010113937.15962-13-ulf.hansson@linaro.org> <20191024163257.GC22036@bogus> <20191025082852.GA4867@e121166-lin.cambridge.arm.com> In-Reply-To: <20191025082852.GA4867@e121166-lin.cambridge.arm.com> From: Ulf Hansson Date: Fri, 25 Oct 2019 16:13:05 +0200 Message-ID: Subject: Re: [PATCH 12/13] cpuidle: psci: Manage runtime PM in the idle path To: Lorenzo Pieralisi Cc: Sudeep Holla , "Rafael J . Wysocki" , Daniel Lezcano , Mark Rutland , Lina Iyer , Linux PM , Rob Herring , Vincent Guittot , Stephen Boyd , Bjorn Andersson , Kevin Hilman , Linux ARM , linux-arm-msm Content-Type: text/plain; charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri, 25 Oct 2019 at 10:29, Lorenzo Pieralisi wrote: > > On Thu, Oct 24, 2019 at 07:00:38PM +0200, Ulf Hansson wrote: > > On Thu, 24 Oct 2019 at 18:33, Sudeep Holla wrote: > > > > > > On Thu, Oct 10, 2019 at 01:39:36PM +0200, Ulf Hansson wrote: > > > > In case we have succeeded to attach a CPU to its PM domain, let's deploy > > > > runtime PM support for the corresponding attached device, to allow the CPU > > > > to be powered-managed accordingly. > > > > > > > > To set the triggering point for when runtime PM reference counting should > > > > be done, let's store the index of deepest idle state for the CPU in the per > > > > CPU struct. Then use this index to compare the selected idle state index > > > > when entering idle, as to understand whether runtime PM reference counting > > > > is needed or not. > > > > > > > > Note that, from the hierarchical point view, there may be good reasons to > > > > do runtime PM reference counting even on shallower idle states, but at this > > > > point this isn't supported, mainly due to limitations set by the generic PM > > > > domain. > > > > > > > > Signed-off-by: Ulf Hansson > > > > --- > > > > drivers/cpuidle/cpuidle-psci.c | 21 +++++++++++++++++++-- > > > > 1 file changed, 19 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/cpuidle/cpuidle-psci.c b/drivers/cpuidle/cpuidle-psci.c > > > > index 1510422c7a53..0919b40c1a85 100644 > > > > --- a/drivers/cpuidle/cpuidle-psci.c > > > > +++ b/drivers/cpuidle/cpuidle-psci.c > > > > @@ -16,6 +16,7 @@ > > > > #include > > > > #include > > > > #include > > > > +#include > > > > #include > > > > > > > > #include > > > > @@ -25,6 +26,7 @@ > > > > > > > > struct psci_cpuidle_data { > > > > u32 *psci_states; > > > > + u32 rpm_state_id; > > > > struct device *dev; > > > > }; > > > > > > > > @@ -50,14 +52,28 @@ static int psci_enter_idle_state(struct cpuidle_device *dev, > > > > struct cpuidle_driver *drv, int idx) > > > > { > > > > int ret; > > > > - u32 *states = __this_cpu_read(psci_cpuidle_data.psci_states); > > > > - u32 state = psci_get_domain_state(); > > > > + struct psci_cpuidle_data *data = this_cpu_ptr(&psci_cpuidle_data); > > > > + u32 *states = data->psci_states; > > > > + struct device *pd_dev = data->dev; > > > > + bool runtime_pm = (pd_dev && data->rpm_state_id == idx); > > > > + u32 state; > > > > > > Wonder if we can have separate psci_enter_idle_state for OSI mode so > > > that all these runtime extra check can be reduced ? It will also make > > > sure there's no additional latency for PC mode because of OSI. > > > > Good idea, that's the plan. See previous answer. > > > > Perhaps if I add a patch on top, implementing your suggestion, would > > you be happy with that? > > Separating idle entry functions was the main idea behind moving PSCI > CPUidle into drivers/cpuidle, I don't think that's complicated to > change and given that the series is not queued yet we can make these > changes in the series itself rather than on top. Okay, no problem. I fold in a patch (or amend existing ones, if that is better) into the series that addresses this. Thanks for reviewing and enjoy your weekend! Kind regards Uffe From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD68BCA9EA0 for ; Fri, 25 Oct 2019 14:13:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9030420663 for ; Fri, 25 Oct 2019 14:13:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="WM8Kh+mP"; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=uN8HSzjVWYgOa/f9HwJLZghBIB5LPa4au9Qp6QOM0oM=; b=ArthcGA88HhdUkowvgewCYhDBiNTzwLZ/H++S5aSd5vaac2/AR9cycBpUUEtJpj0KU NOeK19FIS+GhlAof24iqadpNmJIL5sr91qlQVRhzdUCIRYSi4p4grQt2WRPc9GIByScU DvMPeZ+bxXXbxjcSWHR4WCz6x+KqP+cZe/6OVujL1/LdZrujkycjiZHjbhjn8N5siaHT yw2DbXZedCoKPEwQPc2lCSuZmpNlMw/wbYp5Kz0/bLke0tcsL8fCAUuHqI2iGftUAIcV jhFoobNbzpM0aEW5PxU5EZ4QbLejvdKnpznSLIwBLc/M+Mf900GmAKe2B5muRipeQW+z ndyA== X-Gm-Message-State: APjAAAXjj0pncVYh8HQV2GACYz56m5MpE6DHP0kcOfPcMpY+moyJqaoy X9jsQIqAzXhnqtzk2cAa0hH/RLA2Frur19s2SryWGA== X-Google-Smtp-Source: APXvYqwYv7TgejqODhekRI9dDIIRnGtrb3/+jOe+VBk6FoXTRU0DV374nPjN0wfCLfVDZUOhMqwIhHhSA35PTnmR0zY= X-Received: by 2002:a67:7ac5:: with SMTP id v188mr2030243vsc.191.1572012821656; Fri, 25 Oct 2019 07:13:41 -0700 (PDT) MIME-Version: 1.0 References: <20191010113937.15962-1-ulf.hansson@linaro.org> <20191010113937.15962-13-ulf.hansson@linaro.org> <20191024163257.GC22036@bogus> <20191025082852.GA4867@e121166-lin.cambridge.arm.com> In-Reply-To: <20191025082852.GA4867@e121166-lin.cambridge.arm.com> From: Ulf Hansson Date: Fri, 25 Oct 2019 16:13:05 +0200 Message-ID: Subject: Re: [PATCH 12/13] cpuidle: psci: Manage runtime PM in the idle path To: Lorenzo Pieralisi X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191025_071343_354714_0A66EF24 X-CRM114-Status: GOOD ( 25.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Linux PM , Stephen Boyd , linux-arm-msm , Daniel Lezcano , "Rafael J . Wysocki" , Lina Iyer , Bjorn Andersson , Kevin Hilman , Rob Herring , Sudeep Holla , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 25 Oct 2019 at 10:29, Lorenzo Pieralisi wrote: > > On Thu, Oct 24, 2019 at 07:00:38PM +0200, Ulf Hansson wrote: > > On Thu, 24 Oct 2019 at 18:33, Sudeep Holla wrote: > > > > > > On Thu, Oct 10, 2019 at 01:39:36PM +0200, Ulf Hansson wrote: > > > > In case we have succeeded to attach a CPU to its PM domain, let's deploy > > > > runtime PM support for the corresponding attached device, to allow the CPU > > > > to be powered-managed accordingly. > > > > > > > > To set the triggering point for when runtime PM reference counting should > > > > be done, let's store the index of deepest idle state for the CPU in the per > > > > CPU struct. Then use this index to compare the selected idle state index > > > > when entering idle, as to understand whether runtime PM reference counting > > > > is needed or not. > > > > > > > > Note that, from the hierarchical point view, there may be good reasons to > > > > do runtime PM reference counting even on shallower idle states, but at this > > > > point this isn't supported, mainly due to limitations set by the generic PM > > > > domain. > > > > > > > > Signed-off-by: Ulf Hansson > > > > --- > > > > drivers/cpuidle/cpuidle-psci.c | 21 +++++++++++++++++++-- > > > > 1 file changed, 19 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/cpuidle/cpuidle-psci.c b/drivers/cpuidle/cpuidle-psci.c > > > > index 1510422c7a53..0919b40c1a85 100644 > > > > --- a/drivers/cpuidle/cpuidle-psci.c > > > > +++ b/drivers/cpuidle/cpuidle-psci.c > > > > @@ -16,6 +16,7 @@ > > > > #include > > > > #include > > > > #include > > > > +#include > > > > #include > > > > > > > > #include > > > > @@ -25,6 +26,7 @@ > > > > > > > > struct psci_cpuidle_data { > > > > u32 *psci_states; > > > > + u32 rpm_state_id; > > > > struct device *dev; > > > > }; > > > > > > > > @@ -50,14 +52,28 @@ static int psci_enter_idle_state(struct cpuidle_device *dev, > > > > struct cpuidle_driver *drv, int idx) > > > > { > > > > int ret; > > > > - u32 *states = __this_cpu_read(psci_cpuidle_data.psci_states); > > > > - u32 state = psci_get_domain_state(); > > > > + struct psci_cpuidle_data *data = this_cpu_ptr(&psci_cpuidle_data); > > > > + u32 *states = data->psci_states; > > > > + struct device *pd_dev = data->dev; > > > > + bool runtime_pm = (pd_dev && data->rpm_state_id == idx); > > > > + u32 state; > > > > > > Wonder if we can have separate psci_enter_idle_state for OSI mode so > > > that all these runtime extra check can be reduced ? It will also make > > > sure there's no additional latency for PC mode because of OSI. > > > > Good idea, that's the plan. See previous answer. > > > > Perhaps if I add a patch on top, implementing your suggestion, would > > you be happy with that? > > Separating idle entry functions was the main idea behind moving PSCI > CPUidle into drivers/cpuidle, I don't think that's complicated to > change and given that the series is not queued yet we can make these > changes in the series itself rather than on top. Okay, no problem. I fold in a patch (or amend existing ones, if that is better) into the series that addresses this. Thanks for reviewing and enjoy your weekend! Kind regards Uffe _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel