From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753785AbdCPOqC (ORCPT ); Thu, 16 Mar 2017 10:46:02 -0400 Received: from mail-ua0-f177.google.com ([209.85.217.177]:33795 "EHLO mail-ua0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753372AbdCPOqA (ORCPT ); Thu, 16 Mar 2017 10:46:00 -0400 MIME-Version: 1.0 In-Reply-To: <1488611403-30186-2-git-send-email-yong.mao@mediatek.com> References: <1488611403-30186-1-git-send-email-yong.mao@mediatek.com> <1488611403-30186-2-git-send-email-yong.mao@mediatek.com> From: Ulf Hansson Date: Thu, 16 Mar 2017 15:45:53 +0100 Message-ID: Subject: Re: [PATCH] mmc: mediatek: Fixed bug where clock frequency could be set wrong To: Yong Mao Cc: Linus Walleij , Daniel Kurtz , Chaotian Jing , Eddie Huang , "linux-mmc@vger.kernel.org" , srv_heupstream , linux-mediatek@lists.infradead.org, "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4 March 2017 at 08:10, Yong Mao wrote: > From: yong mao > > This patch can fix two issues: > > Issue 1: > In previous code, div may be overflow when setting clock frequency > as f_min. We can use DIV_ROUND_UP to fix this boundary related > issue. > > Issue 2: > In previous code, we can not set the correct clock frequency when > div equals 0xff. > > Signed-off-by: Yong Mao > Signed-off-by: Chaotian Jing > --- > drivers/mmc/host/mtk-sd.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > index 07f3236..3ad5228 100644 > --- a/drivers/mmc/host/mtk-sd.c > +++ b/drivers/mmc/host/mtk-sd.c > @@ -591,7 +591,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) > } > } > sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, > - (mode << 8) | (div % 0xff)); > + (mode << 8) | div); > sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); > while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) > cpu_relax(); > @@ -1692,7 +1692,7 @@ static int msdc_drv_probe(struct platform_device *pdev) > host->src_clk_freq = clk_get_rate(host->src_clk); > /* Set host parameters to mmc */ > mmc->ops = &mt_msdc_ops; > - mmc->f_min = host->src_clk_freq / (4 * 255); > + mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); > > mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; > /* MMC core transfer sizes tunable parameters */ > -- > 1.7.9.5 > Thanks, applied for fixes! Kind regards Uffe From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ulf Hansson Subject: Re: [PATCH] mmc: mediatek: Fixed bug where clock frequency could be set wrong Date: Thu, 16 Mar 2017 15:45:53 +0100 Message-ID: References: <1488611403-30186-1-git-send-email-yong.mao@mediatek.com> <1488611403-30186-2-git-send-email-yong.mao@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: Received: from mail-ua0-f171.google.com ([209.85.217.171]:36722 "EHLO mail-ua0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753408AbdCPOpz (ORCPT ); Thu, 16 Mar 2017 10:45:55 -0400 Received: by mail-ua0-f171.google.com with SMTP id 72so27519915uaf.3 for ; Thu, 16 Mar 2017 07:45:54 -0700 (PDT) In-Reply-To: <1488611403-30186-2-git-send-email-yong.mao@mediatek.com> Sender: linux-mmc-owner@vger.kernel.org List-Id: linux-mmc@vger.kernel.org To: Yong Mao Cc: Linus Walleij , Daniel Kurtz , Chaotian Jing , Eddie Huang , "linux-mmc@vger.kernel.org" , srv_heupstream , linux-mediatek@lists.infradead.org, "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" On 4 March 2017 at 08:10, Yong Mao wrote: > From: yong mao > > This patch can fix two issues: > > Issue 1: > In previous code, div may be overflow when setting clock frequency > as f_min. We can use DIV_ROUND_UP to fix this boundary related > issue. > > Issue 2: > In previous code, we can not set the correct clock frequency when > div equals 0xff. > > Signed-off-by: Yong Mao > Signed-off-by: Chaotian Jing > --- > drivers/mmc/host/mtk-sd.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > index 07f3236..3ad5228 100644 > --- a/drivers/mmc/host/mtk-sd.c > +++ b/drivers/mmc/host/mtk-sd.c > @@ -591,7 +591,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) > } > } > sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, > - (mode << 8) | (div % 0xff)); > + (mode << 8) | div); > sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); > while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) > cpu_relax(); > @@ -1692,7 +1692,7 @@ static int msdc_drv_probe(struct platform_device *pdev) > host->src_clk_freq = clk_get_rate(host->src_clk); > /* Set host parameters to mmc */ > mmc->ops = &mt_msdc_ops; > - mmc->f_min = host->src_clk_freq / (4 * 255); > + mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); > > mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; > /* MMC core transfer sizes tunable parameters */ > -- > 1.7.9.5 > Thanks, applied for fixes! Kind regards Uffe From mboxrd@z Thu Jan 1 00:00:00 1970 From: ulf.hansson@linaro.org (Ulf Hansson) Date: Thu, 16 Mar 2017 15:45:53 +0100 Subject: [PATCH] mmc: mediatek: Fixed bug where clock frequency could be set wrong In-Reply-To: <1488611403-30186-2-git-send-email-yong.mao@mediatek.com> References: <1488611403-30186-1-git-send-email-yong.mao@mediatek.com> <1488611403-30186-2-git-send-email-yong.mao@mediatek.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 4 March 2017 at 08:10, Yong Mao wrote: > From: yong mao > > This patch can fix two issues: > > Issue 1: > In previous code, div may be overflow when setting clock frequency > as f_min. We can use DIV_ROUND_UP to fix this boundary related > issue. > > Issue 2: > In previous code, we can not set the correct clock frequency when > div equals 0xff. > > Signed-off-by: Yong Mao > Signed-off-by: Chaotian Jing > --- > drivers/mmc/host/mtk-sd.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > index 07f3236..3ad5228 100644 > --- a/drivers/mmc/host/mtk-sd.c > +++ b/drivers/mmc/host/mtk-sd.c > @@ -591,7 +591,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) > } > } > sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, > - (mode << 8) | (div % 0xff)); > + (mode << 8) | div); > sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); > while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) > cpu_relax(); > @@ -1692,7 +1692,7 @@ static int msdc_drv_probe(struct platform_device *pdev) > host->src_clk_freq = clk_get_rate(host->src_clk); > /* Set host parameters to mmc */ > mmc->ops = &mt_msdc_ops; > - mmc->f_min = host->src_clk_freq / (4 * 255); > + mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); > > mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; > /* MMC core transfer sizes tunable parameters */ > -- > 1.7.9.5 > Thanks, applied for fixes! Kind regards Uffe