From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0FC9C2BA19 for ; Wed, 15 Apr 2020 10:45:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B9DD20737 for ; Wed, 15 Apr 2020 10:45:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Iu2LC+jH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2896567AbgDOKpV (ORCPT ); Wed, 15 Apr 2020 06:45:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2896476AbgDOKXh (ORCPT ); Wed, 15 Apr 2020 06:23:37 -0400 Received: from mail-vs1-xe42.google.com (mail-vs1-xe42.google.com [IPv6:2607:f8b0:4864:20::e42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F54CC0610D6 for ; Wed, 15 Apr 2020 03:22:28 -0700 (PDT) Received: by mail-vs1-xe42.google.com with SMTP id r7so1888583vso.2 for ; Wed, 15 Apr 2020 03:22:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=IjEZMO0SU7rIu8lnCDeDsF/aghcVDa3TqsVdoRMbMEE=; b=Iu2LC+jHJsIB6vZbtwVzRAfa2cQkr1qZliuN7B1CB4zXFPPDwe6389BCY8Ja757gO3 l68GmGiTtRlb8f1fUF/0mYUsfNC1wROzXtlhIE3iEmwRmL0jBFp8J4bNS+zxPSUYohuz lXkqsxV8CkLEQz+xoxviB6mgVEfI18CHQU9lmMMsdREkwKEtAPXbyjM5kJx4z3PY3dqU uAox33zcxIKYCiGaz1oEWbtCgkqdOZZceB95RMK9yeOt+gALZbuEBiia1kHhoakqY8XH yBrpyq6EsWsJJj7OpZKpPXLdM1O21iP8I1e+MJ+Gs6m7p3KZW9LvguEUwaJNh/m454c8 qclA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=IjEZMO0SU7rIu8lnCDeDsF/aghcVDa3TqsVdoRMbMEE=; b=Xk9vGr/L+jNN1JYbb+1k/bHcQdL//Xr3QceSonOfI1REgRISCSmcasbx4fXv6D43sv 3njZsly5G0DNRa9+YW1dZQHgf2zICv9rM90aKTW4vyJX2SnE4w17hHL+aaCP+KIBxuX4 V2z+Nk51J1bhe7Zl9wO0TIzKQJuwc2cHdJ4IwGKyJmL88oveNWds7l6QticzAHa5G4Wr spEchg4SgudMd668G/becAPfREACqvPK4DeSEJ7ka+flBQSDkEwZBmoOA6TqH57goSGY Gik8JHcdx5ukJ6Qhw/5oDzYoEuRkvs9QASDuRHXiloNXXRtXw62gYmbWzw5nd8+oLpXy UJQw== X-Gm-Message-State: AGi0Pubxail1U8RlsoRJMHaP196mbcTMXLPnCiLGzDfNk9tBgUn/TbcL SgPNfXzmFDK3BtDrHYCOVinWv7G2HuPxKmP7woYxeg== X-Google-Smtp-Source: APiQypILzw+Mgfa0IPeRWLq+ed7OhGK1AmhdY/ISSlbVg17eVUjcHARL3Ijh9uyzWw4vScHNgOR0sy1q0m+qUlp2P5Y= X-Received: by 2002:a67:11c4:: with SMTP id 187mr3793955vsr.34.1586946147163; Wed, 15 Apr 2020 03:22:27 -0700 (PDT) MIME-Version: 1.0 References: <20200408072105.422-1-yamada.masahiro@socionext.com> <20200408072105.422-2-yamada.masahiro@socionext.com> <3cc8c9b8-b957-2fef-d6da-47980d1926aa@intel.com> In-Reply-To: <3cc8c9b8-b957-2fef-d6da-47980d1926aa@intel.com> From: Ulf Hansson Date: Wed, 15 Apr 2020 12:21:51 +0200 Message-ID: Subject: Re: [PATCH 2/2] mmc: sdhci: use FIELD_GET/PREP for capabilities bit masks To: Masahiro Yamada Cc: "linux-mmc@vger.kernel.org" , Linux Kernel Mailing List , masahiroy@kernel.org, Alexandre Belloni , Fabio Estevam , Adrian Hunter , Ludovic Desroches , NXP Linux Team , Nicolas Ferre , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Linux ARM Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 15 Apr 2020 at 11:35, Adrian Hunter wrote: > > On 8/04/20 10:21 am, Masahiro Yamada wrote: > > Use FIELD_GET and FIELD_PREP to get access to the register fields. > > Delete the shift macros. I used GENMASK() for touched macros. > > That has the side-effect of changing the constants to 64-bit on 64-bit > platforms, which needs to be mentioned in the commit message. > > > > > Signed-off-by: Masahiro Yamada > > Apart from above: > > Acked-by: Adrian Hunter Applied for next, by amending the changelog according to the suggestion by Adrian. Kind regards Uffe > > > --- > > > > drivers/mmc/host/sdhci-esdhc-imx.c | 4 +++- > > drivers/mmc/host/sdhci-of-at91.c | 5 +++-- > > drivers/mmc/host/sdhci-pci-core.c | 8 ++------ > > drivers/mmc/host/sdhci.c | 19 +++++++------------ > > drivers/mmc/host/sdhci.h | 17 ++++++----------- > > 5 files changed, 21 insertions(+), 32 deletions(-) > > > > diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c > > index 5ec8e4bf1ac7..38cd83118082 100644 > > --- a/drivers/mmc/host/sdhci-esdhc-imx.c > > +++ b/drivers/mmc/host/sdhci-esdhc-imx.c > > @@ -8,6 +8,7 @@ > > * Author: Wolfram Sang > > */ > > > > +#include > > #include > > #include > > #include > > @@ -399,7 +400,8 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) > > val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 > > | SDHCI_SUPPORT_SDR50 > > | SDHCI_USE_SDR50_TUNING > > - | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); > > + | FIELD_PREP(SDHCI_RETUNING_MODE_MASK, > > + SDHCI_TUNING_MODE_3); > > > > if (imx_data->socdata->flags & ESDHC_FLAG_HS400) > > val |= SDHCI_SUPPORT_HS400; > > diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c > > index c79bff5e2280..25f4e0f4f53b 100644 > > --- a/drivers/mmc/host/sdhci-of-at91.c > > +++ b/drivers/mmc/host/sdhci-of-at91.c > > @@ -6,6 +6,7 @@ > > * 2015 Ludovic Desroches > > */ > > > > +#include > > #include > > #include > > #include > > @@ -179,9 +180,9 @@ static int sdhci_at91_set_clks_presets(struct device *dev) > > clk_mul = gck_rate / clk_base_rate - 1; > > > > caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK; > > - caps0 |= (clk_base << SDHCI_CLOCK_BASE_SHIFT) & SDHCI_CLOCK_V3_BASE_MASK; > > + caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base); > > caps1 &= ~SDHCI_CLOCK_MUL_MASK; > > - caps1 |= (clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK; > > + caps1 |= FIELD_PREP(SDHCI_CLOCK_MUL_MASK, clk_mul); > > /* Set capabilities in r/w mode. */ > > writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); > > writel(caps0, host->ioaddr + SDHCI_CAPABILITIES); > > diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c > > index 525de2454a4d..a98c9476bfc8 100644 > > --- a/drivers/mmc/host/sdhci-pci-core.c > > +++ b/drivers/mmc/host/sdhci-pci-core.c > > @@ -249,12 +249,8 @@ static int ricoh_probe(struct sdhci_pci_chip *chip) > > static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) > > { > > slot->host->caps = > > - ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) > > - & SDHCI_TIMEOUT_CLK_MASK) | > > - > > - ((0x21 << SDHCI_CLOCK_BASE_SHIFT) > > - & SDHCI_CLOCK_BASE_MASK) | > > - > > + FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | > > + FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | > > SDHCI_TIMEOUT_CLK_UNIT | > > SDHCI_CAN_VDD_330 | > > SDHCI_CAN_DO_HISPD | > > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > > index 3f716466fcfd..344a7e0e33fe 100644 > > --- a/drivers/mmc/host/sdhci.c > > +++ b/drivers/mmc/host/sdhci.c > > @@ -4117,11 +4117,9 @@ int sdhci_setup_host(struct sdhci_host *host) > > } > > > > if (host->version >= SDHCI_SPEC_300) > > - host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK) > > - >> SDHCI_CLOCK_BASE_SHIFT; > > + host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps); > > else > > - host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK) > > - >> SDHCI_CLOCK_BASE_SHIFT; > > + host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps); > > > > host->max_clk *= 1000000; > > if (host->max_clk == 0 || host->quirks & > > @@ -4139,8 +4137,7 @@ int sdhci_setup_host(struct sdhci_host *host) > > * In case of Host Controller v3.00, find out whether clock > > * multiplier is supported. > > */ > > - host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >> > > - SDHCI_CLOCK_MUL_SHIFT; > > + host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1); > > > > /* > > * In case the value in Clock Multiplier is 0, then programmable > > @@ -4173,8 +4170,7 @@ int sdhci_setup_host(struct sdhci_host *host) > > mmc->f_max = max_clk; > > > > if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { > > - host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >> > > - SDHCI_TIMEOUT_CLK_SHIFT; > > + host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps); > > > > if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) > > host->timeout_clk *= 1000; > > @@ -4326,8 +4322,8 @@ int sdhci_setup_host(struct sdhci_host *host) > > mmc->caps |= MMC_CAP_DRIVER_TYPE_D; > > > > /* Initial value for re-tuning timer count */ > > - host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >> > > - SDHCI_RETUNING_TIMER_COUNT_SHIFT; > > + host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK, > > + host->caps1); > > > > /* > > * In case Re-tuning Timer is not disabled, the actual value of > > @@ -4337,8 +4333,7 @@ int sdhci_setup_host(struct sdhci_host *host) > > host->tuning_count = 1 << (host->tuning_count - 1); > > > > /* Re-tuning mode supported by the Host Controller */ > > - host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >> > > - SDHCI_RETUNING_MODE_SHIFT; > > + host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1); > > > > ocr_avail = 0; > > > > diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h > > index b786b68e0302..d7f1441b0fc3 100644 > > --- a/drivers/mmc/host/sdhci.h > > +++ b/drivers/mmc/host/sdhci.h > > @@ -200,12 +200,10 @@ > > #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 > > > > #define SDHCI_CAPABILITIES 0x40 > > -#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F > > -#define SDHCI_TIMEOUT_CLK_SHIFT 0 > > +#define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0) > > #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 > > -#define SDHCI_CLOCK_BASE_MASK 0x00003F00 > > -#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 > > -#define SDHCI_CLOCK_BASE_SHIFT 8 > > +#define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8) > > +#define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8) > > #define SDHCI_MAX_BLOCK_MASK 0x00030000 > > #define SDHCI_MAX_BLOCK_SHIFT 16 > > #define SDHCI_CAN_DO_8BIT 0x00040000 > > @@ -227,13 +225,10 @@ > > #define SDHCI_DRIVER_TYPE_A 0x00000010 > > #define SDHCI_DRIVER_TYPE_C 0x00000020 > > #define SDHCI_DRIVER_TYPE_D 0x00000040 > > -#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 > > -#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 > > +#define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8) > > #define SDHCI_USE_SDR50_TUNING 0x00002000 > > -#define SDHCI_RETUNING_MODE_MASK 0x0000C000 > > -#define SDHCI_RETUNING_MODE_SHIFT 14 > > -#define SDHCI_CLOCK_MUL_MASK 0x00FF0000 > > -#define SDHCI_CLOCK_MUL_SHIFT 16 > > +#define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) > > +#define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) > > #define SDHCI_CAN_DO_ADMA3 0x08000000 > > #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ > > > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3274DC2BA19 for ; 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Wed, 15 Apr 2020 03:22:27 -0700 (PDT) MIME-Version: 1.0 References: <20200408072105.422-1-yamada.masahiro@socionext.com> <20200408072105.422-2-yamada.masahiro@socionext.com> <3cc8c9b8-b957-2fef-d6da-47980d1926aa@intel.com> In-Reply-To: <3cc8c9b8-b957-2fef-d6da-47980d1926aa@intel.com> From: Ulf Hansson Date: Wed, 15 Apr 2020 12:21:51 +0200 Message-ID: Subject: Re: [PATCH 2/2] mmc: sdhci: use FIELD_GET/PREP for capabilities bit masks To: Masahiro Yamada X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200415_032228_995831_36EB93B2 X-CRM114-Status: GOOD ( 23.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Belloni , Shawn Guo , masahiroy@kernel.org, "linux-mmc@vger.kernel.org" , Linux Kernel Mailing List , Adrian Hunter , Ludovic Desroches , NXP Linux Team , Pengutronix Kernel Team , Fabio Estevam , Sascha Hauer , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 15 Apr 2020 at 11:35, Adrian Hunter wrote: > > On 8/04/20 10:21 am, Masahiro Yamada wrote: > > Use FIELD_GET and FIELD_PREP to get access to the register fields. > > Delete the shift macros. I used GENMASK() for touched macros. > > That has the side-effect of changing the constants to 64-bit on 64-bit > platforms, which needs to be mentioned in the commit message. > > > > > Signed-off-by: Masahiro Yamada > > Apart from above: > > Acked-by: Adrian Hunter Applied for next, by amending the changelog according to the suggestion by Adrian. Kind regards Uffe > > > --- > > > > drivers/mmc/host/sdhci-esdhc-imx.c | 4 +++- > > drivers/mmc/host/sdhci-of-at91.c | 5 +++-- > > drivers/mmc/host/sdhci-pci-core.c | 8 ++------ > > drivers/mmc/host/sdhci.c | 19 +++++++------------ > > drivers/mmc/host/sdhci.h | 17 ++++++----------- > > 5 files changed, 21 insertions(+), 32 deletions(-) > > > > diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c > > index 5ec8e4bf1ac7..38cd83118082 100644 > > --- a/drivers/mmc/host/sdhci-esdhc-imx.c > > +++ b/drivers/mmc/host/sdhci-esdhc-imx.c > > @@ -8,6 +8,7 @@ > > * Author: Wolfram Sang > > */ > > > > +#include > > #include > > #include > > #include > > @@ -399,7 +400,8 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) > > val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 > > | SDHCI_SUPPORT_SDR50 > > | SDHCI_USE_SDR50_TUNING > > - | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT); > > + | FIELD_PREP(SDHCI_RETUNING_MODE_MASK, > > + SDHCI_TUNING_MODE_3); > > > > if (imx_data->socdata->flags & ESDHC_FLAG_HS400) > > val |= SDHCI_SUPPORT_HS400; > > diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c > > index c79bff5e2280..25f4e0f4f53b 100644 > > --- a/drivers/mmc/host/sdhci-of-at91.c > > +++ b/drivers/mmc/host/sdhci-of-at91.c > > @@ -6,6 +6,7 @@ > > * 2015 Ludovic Desroches > > */ > > > > +#include > > #include > > #include > > #include > > @@ -179,9 +180,9 @@ static int sdhci_at91_set_clks_presets(struct device *dev) > > clk_mul = gck_rate / clk_base_rate - 1; > > > > caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK; > > - caps0 |= (clk_base << SDHCI_CLOCK_BASE_SHIFT) & SDHCI_CLOCK_V3_BASE_MASK; > > + caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base); > > caps1 &= ~SDHCI_CLOCK_MUL_MASK; > > - caps1 |= (clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK; > > + caps1 |= FIELD_PREP(SDHCI_CLOCK_MUL_MASK, clk_mul); > > /* Set capabilities in r/w mode. */ > > writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); > > writel(caps0, host->ioaddr + SDHCI_CAPABILITIES); > > diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c > > index 525de2454a4d..a98c9476bfc8 100644 > > --- a/drivers/mmc/host/sdhci-pci-core.c > > +++ b/drivers/mmc/host/sdhci-pci-core.c > > @@ -249,12 +249,8 @@ static int ricoh_probe(struct sdhci_pci_chip *chip) > > static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) > > { > > slot->host->caps = > > - ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) > > - & SDHCI_TIMEOUT_CLK_MASK) | > > - > > - ((0x21 << SDHCI_CLOCK_BASE_SHIFT) > > - & SDHCI_CLOCK_BASE_MASK) | > > - > > + FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | > > + FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | > > SDHCI_TIMEOUT_CLK_UNIT | > > SDHCI_CAN_VDD_330 | > > SDHCI_CAN_DO_HISPD | > > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c > > index 3f716466fcfd..344a7e0e33fe 100644 > > --- a/drivers/mmc/host/sdhci.c > > +++ b/drivers/mmc/host/sdhci.c > > @@ -4117,11 +4117,9 @@ int sdhci_setup_host(struct sdhci_host *host) > > } > > > > if (host->version >= SDHCI_SPEC_300) > > - host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK) > > - >> SDHCI_CLOCK_BASE_SHIFT; > > + host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps); > > else > > - host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK) > > - >> SDHCI_CLOCK_BASE_SHIFT; > > + host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps); > > > > host->max_clk *= 1000000; > > if (host->max_clk == 0 || host->quirks & > > @@ -4139,8 +4137,7 @@ int sdhci_setup_host(struct sdhci_host *host) > > * In case of Host Controller v3.00, find out whether clock > > * multiplier is supported. > > */ > > - host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >> > > - SDHCI_CLOCK_MUL_SHIFT; > > + host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1); > > > > /* > > * In case the value in Clock Multiplier is 0, then programmable > > @@ -4173,8 +4170,7 @@ int sdhci_setup_host(struct sdhci_host *host) > > mmc->f_max = max_clk; > > > > if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { > > - host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >> > > - SDHCI_TIMEOUT_CLK_SHIFT; > > + host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps); > > > > if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) > > host->timeout_clk *= 1000; > > @@ -4326,8 +4322,8 @@ int sdhci_setup_host(struct sdhci_host *host) > > mmc->caps |= MMC_CAP_DRIVER_TYPE_D; > > > > /* Initial value for re-tuning timer count */ > > - host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >> > > - SDHCI_RETUNING_TIMER_COUNT_SHIFT; > > + host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK, > > + host->caps1); > > > > /* > > * In case Re-tuning Timer is not disabled, the actual value of > > @@ -4337,8 +4333,7 @@ int sdhci_setup_host(struct sdhci_host *host) > > host->tuning_count = 1 << (host->tuning_count - 1); > > > > /* Re-tuning mode supported by the Host Controller */ > > - host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >> > > - SDHCI_RETUNING_MODE_SHIFT; > > + host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1); > > > > ocr_avail = 0; > > > > diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h > > index b786b68e0302..d7f1441b0fc3 100644 > > --- a/drivers/mmc/host/sdhci.h > > +++ b/drivers/mmc/host/sdhci.h > > @@ -200,12 +200,10 @@ > > #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 > > > > #define SDHCI_CAPABILITIES 0x40 > > -#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F > > -#define SDHCI_TIMEOUT_CLK_SHIFT 0 > > +#define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0) > > #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 > > -#define SDHCI_CLOCK_BASE_MASK 0x00003F00 > > -#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 > > -#define SDHCI_CLOCK_BASE_SHIFT 8 > > +#define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8) > > +#define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8) > > #define SDHCI_MAX_BLOCK_MASK 0x00030000 > > #define SDHCI_MAX_BLOCK_SHIFT 16 > > #define SDHCI_CAN_DO_8BIT 0x00040000 > > @@ -227,13 +225,10 @@ > > #define SDHCI_DRIVER_TYPE_A 0x00000010 > > #define SDHCI_DRIVER_TYPE_C 0x00000020 > > #define SDHCI_DRIVER_TYPE_D 0x00000040 > > -#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00 > > -#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8 > > +#define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8) > > #define SDHCI_USE_SDR50_TUNING 0x00002000 > > -#define SDHCI_RETUNING_MODE_MASK 0x0000C000 > > -#define SDHCI_RETUNING_MODE_SHIFT 14 > > -#define SDHCI_CLOCK_MUL_MASK 0x00FF0000 > > -#define SDHCI_CLOCK_MUL_SHIFT 16 > > +#define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) > > +#define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) > > #define SDHCI_CAN_DO_ADMA3 0x08000000 > > #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ > > > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel