From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42D04C432BE for ; Tue, 3 Aug 2021 11:41:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2E9FF60ED6 for ; Tue, 3 Aug 2021 11:41:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235942AbhHCLls (ORCPT ); Tue, 3 Aug 2021 07:41:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235945AbhHCLlm (ORCPT ); Tue, 3 Aug 2021 07:41:42 -0400 Received: from mail-ua1-x92d.google.com (mail-ua1-x92d.google.com [IPv6:2607:f8b0:4864:20::92d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EA0BC061799 for ; Tue, 3 Aug 2021 04:41:28 -0700 (PDT) Received: by mail-ua1-x92d.google.com with SMTP id 79so8065190uau.9 for ; Tue, 03 Aug 2021 04:41:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=q9weUQNZb8zSNK5Fi3st7B7Mx/yd5pLorJlvNfQAB7M=; b=kfcBVwLo2v4t80n4OumhhW192grQ72/pi1j+v0NLCEfgB2B7gJ5T9Az1FmJquZjew+ pV28mDG/VvEawMLGiiyTlwSYOpy4tuqlTl0HdBcu/rJlfa2S6EkvhYc9Gzp+5ly2XoMA JmTF+5CQu64TXVH5tUYJTSG/JR3Y/SZutL+lx90PjFoWTf5hBfWsz/Szga2pgnAGiZnr sPZX1K4poC/VjFsxpeM5+nic+zPT9zJwux1h+BGJA5K8BL6/6Zh77XjkUnLJYtocjyeK 9zwoiTXM6DVIqKTxJwvhgIZGQNPFBomEZ57Cjfd/vhcTWVXvqrmhZQBBHonRj5c9Unfi KjWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=q9weUQNZb8zSNK5Fi3st7B7Mx/yd5pLorJlvNfQAB7M=; b=UYQAAWrtTk/AtY4EPy1gsxD9J+oNlZH85UQI2KydfjhJvmY3T1byhxNx4DKMET8vgW UahRvg8V3/6hykmLiF7F40vM7904cA3/r5SuI4i7KA27eX7Luvk3j6FLQh0zRzraUeZK NimePumTuPX9kiz2MkOuvtiqKE8EAIVkTnMSm/Ig7V+Upsu/IdMLBjIJu2H5fSUOt1tQ 7dISZOOAPlVidavjMxeV9j4ERjLTx+AA5ntC8ZwCcKHsDEh1jyKb+g/dye84a7A8fAKv Yjvmb1WJ0zcZtNoYRV3/X1XRgssqVJRy4ZzC1npfO1rQGnFFC69wBDytvZQlNSgYbb/A C2zg== X-Gm-Message-State: AOAM531xFIHanwhU5/zuUC89NjiiF+qRzShKOBj4+DO9qn0hUGzvZtXN fE3SoUcVlVOxjYJxPmAGlo5PF683FHmIsCHZ74lSZw== X-Google-Smtp-Source: ABdhPJyMm8jbzan+OPnDFk8P5ouN4DVyswFjAchUVuSljur2ivO50vwXOgB9rQG9t/IlQF5od7rElB1Vo73792CVc80= X-Received: by 2002:ab0:4e22:: with SMTP id g34mr14114826uah.17.1627990887450; Tue, 03 Aug 2021 04:41:27 -0700 (PDT) MIME-Version: 1.0 References: <20210730144922.29111-1-semen.protsenko@linaro.org> <20210730144922.29111-5-semen.protsenko@linaro.org> <7364ccb2-70da-6400-ae6d-6a30171b6678@canonical.com> In-Reply-To: <7364ccb2-70da-6400-ae6d-6a30171b6678@canonical.com> From: Sam Protsenko Date: Tue, 3 Aug 2021 14:41:15 +0300 Message-ID: Subject: Re: [PATCH 04/12] tty: serial: samsung: Init USI to keep clocks running To: Krzysztof Kozlowski Cc: Sylwester Nawrocki , Chanwoo Choi , Linus Walleij , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree , linux-arm Mailing List , linux-clk , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux Samsung SOC , "open list:SERIAL DRIVERS" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Tue, 3 Aug 2021 at 10:37, Krzysztof Kozlowski wrote: > > On 03/08/2021 01:06, Sam Protsenko wrote: > > (...) > > >>> diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h > >>> index f6c3323fc4c5..013c2646863e 100644 > >>> --- a/include/linux/serial_s3c.h > >>> +++ b/include/linux/serial_s3c.h > >>> @@ -28,6 +28,15 @@ > >>> #define S3C2410_UFSTAT (0x18) > >>> #define S3C2410_UMSTAT (0x1C) > >>> > >>> +/* USI Control Register offset */ > >>> +#define USI_CON (0xC4) > >>> +/* USI Option Register offset */ > >>> +#define USI_OPTION (0xC8) > >>> +/* USI_CON[0] = 0b0: clear USI global software reset (Active High) */ > >>> +#define USI_RESET (0<<0) > >> > >> Just 0x0. I understand you wanted to hint it is a bit field, but the > >> shift of 0 actually creates more questions. > >> > > > > After some consideration I decided to adhere to existing style and do > > something like this (in v2): > > > > 8<--------------------------------------------------------------------->8 > > #define USI_CON (0xC4) > > #define USI_OPTION (0xC8) > > > > #define USI_CON_RESET_CLEAR (0<<0) > > #define USI_CON_RESET_SET (1<<0) > > #define USI_CON_RESET_MASK (1<<0) > > > > #define USI_OPTION_HWACG_CLKREQ_ON (1<<1) > > #define USI_OPTION_HWACG_CLKSTOP_ON (1<<2) > > #define USI_OPTION_HWACG_MASK (3<<1) > > 8<--------------------------------------------------------------------->8 > > > > The whole reason for those comments was missing public TRM. But in the > > end I decided it just looks ugly. Also, this way I can do RMW > > operation (discussed above) in more logical way. > > > > Please let me know if code snippets above look good to you. > > Please skip the USI_CON_RESET_CLEAR. There is no such pattern in the > code. Clearing bit is an obvious operation and such code is already > everywhere: > val &= ~USI_CON_RESET > > (or &= ~USI_RESET_MASK) > > Therefore for USI_CON_RESET only: > #define USI_CON_RESET (1<<0) > #define USI_CON_RESET_MASK (1<<0) > Sure, I'll make it so. > > Best regards, > Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCE0AC4338F for ; Tue, 3 Aug 2021 11:55:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 97B4560C3F for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 3 Aug 2021 at 10:37, Krzysztof Kozlowski wrote: > > On 03/08/2021 01:06, Sam Protsenko wrote: > > (...) > > >>> diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h > >>> index f6c3323fc4c5..013c2646863e 100644 > >>> --- a/include/linux/serial_s3c.h > >>> +++ b/include/linux/serial_s3c.h > >>> @@ -28,6 +28,15 @@ > >>> #define S3C2410_UFSTAT (0x18) > >>> #define S3C2410_UMSTAT (0x1C) > >>> > >>> +/* USI Control Register offset */ > >>> +#define USI_CON (0xC4) > >>> +/* USI Option Register offset */ > >>> +#define USI_OPTION (0xC8) > >>> +/* USI_CON[0] = 0b0: clear USI global software reset (Active High) */ > >>> +#define USI_RESET (0<<0) > >> > >> Just 0x0. I understand you wanted to hint it is a bit field, but the > >> shift of 0 actually creates more questions. > >> > > > > After some consideration I decided to adhere to existing style and do > > something like this (in v2): > > > > 8<--------------------------------------------------------------------->8 > > #define USI_CON (0xC4) > > #define USI_OPTION (0xC8) > > > > #define USI_CON_RESET_CLEAR (0<<0) > > #define USI_CON_RESET_SET (1<<0) > > #define USI_CON_RESET_MASK (1<<0) > > > > #define USI_OPTION_HWACG_CLKREQ_ON (1<<1) > > #define USI_OPTION_HWACG_CLKSTOP_ON (1<<2) > > #define USI_OPTION_HWACG_MASK (3<<1) > > 8<--------------------------------------------------------------------->8 > > > > The whole reason for those comments was missing public TRM. But in the > > end I decided it just looks ugly. Also, this way I can do RMW > > operation (discussed above) in more logical way. > > > > Please let me know if code snippets above look good to you. > > Please skip the USI_CON_RESET_CLEAR. There is no such pattern in the > code. Clearing bit is an obvious operation and such code is already > everywhere: > val &= ~USI_CON_RESET > > (or &= ~USI_RESET_MASK) > > Therefore for USI_CON_RESET only: > #define USI_CON_RESET (1<<0) > #define USI_CON_RESET_MASK (1<<0) > Sure, I'll make it so. > > Best regards, > Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel