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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Maxime On Fri, 25 Sep 2020 at 14:00, Maxime Ripard wrote: > > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels > per clock cycle, and cannot deal with odd timings. > > Let's reject any mode with such timings. > > Signed-off-by: Maxime Ripard It's unsupported due to the architecture rather than broken. I'd hope the compiler would convert "% 2" to "& 1" in these cases, but it's not a critical performance path anyway. Reviewed-by: Dave Stevenson > --- > drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++++++++ > drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++ > 2 files changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > index 1c4dc774d56e..acfb4e235214 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > @@ -879,6 +879,11 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, > struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > unsigned long long pixel_rate = mode->clock * 1000; > > + if (vc4_hdmi->variant->broken_odd_h_timings && > + ((mode->hdisplay % 2) || (mode->hsync_start % 2) || > + (mode->hsync_end % 2) || (mode->htotal % 2))) > + return -EINVAL; > + > if (mode->flags & DRM_MODE_FLAG_DBLCLK) > pixel_rate *= 2; > > @@ -901,6 +906,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, > { > struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > > + if (vc4_hdmi->variant->broken_odd_h_timings && > + ((mode->hdisplay % 2) || (mode->hsync_start % 2) || > + (mode->hsync_end % 2) || (mode->htotal % 2))) > + return MODE_H_ILLEGAL; > + > if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) > return MODE_CLOCK_HIGH; > > @@ -1950,6 +1960,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { > PHY_LANE_2, > PHY_LANE_CK, > }, > + .broken_odd_h_timings = true, > > .init_resources = vc5_hdmi_init_resources, > .csc_setup = vc5_hdmi_csc_setup, > @@ -1975,6 +1986,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { > PHY_LANE_CK, > PHY_LANE_2, > }, > + .broken_odd_h_timings = true, > > .init_resources = vc5_hdmi_init_resources, > .csc_setup = vc5_hdmi_csc_setup, > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h > index af45b0d81dec..40e51ece8efe 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.h > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h > @@ -62,6 +62,9 @@ struct vc4_hdmi_variant { > */ > enum vc4_hdmi_phy_channel phy_lane_mapping[4]; > > + /* The BCM2711 cannot deal with odd horizontal pixel timings */ > + bool broken_odd_h_timings; > + > /* Callback to get the resources (memory region, interrupts, > * clocks, etc) for that variant. > */ > -- > 2.26.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23261C388F7 for ; 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Wed, 28 Oct 2020 06:42:37 -0700 (PDT) MIME-Version: 1.0 References: <20200925130044.574220-1-maxime@cerno.tech> In-Reply-To: <20200925130044.574220-1-maxime@cerno.tech> From: Dave Stevenson Date: Wed, 28 Oct 2020 13:42:20 +0000 Message-ID: Subject: Re: [PATCH] drm/vc4: hdmi: Block odd horizontal timings To: Maxime Ripard X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tim Gover , David Airlie , DRI Development , bcm-kernel-feedback-list@broadcom.com, linux-rpi-kernel@lists.infradead.org, Thomas Zimmermann , Daniel Vetter , Phil Elwell , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Maxime On Fri, 25 Sep 2020 at 14:00, Maxime Ripard wrote: > > The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels > per clock cycle, and cannot deal with odd timings. > > Let's reject any mode with such timings. > > Signed-off-by: Maxime Ripard It's unsupported due to the architecture rather than broken. I'd hope the compiler would convert "% 2" to "& 1" in these cases, but it's not a critical performance path anyway. Reviewed-by: Dave Stevenson > --- > drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++++++++ > drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++ > 2 files changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c > index 1c4dc774d56e..acfb4e235214 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.c > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c > @@ -879,6 +879,11 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, > struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > unsigned long long pixel_rate = mode->clock * 1000; > > + if (vc4_hdmi->variant->broken_odd_h_timings && > + ((mode->hdisplay % 2) || (mode->hsync_start % 2) || > + (mode->hsync_end % 2) || (mode->htotal % 2))) > + return -EINVAL; > + > if (mode->flags & DRM_MODE_FLAG_DBLCLK) > pixel_rate *= 2; > > @@ -901,6 +906,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, > { > struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); > > + if (vc4_hdmi->variant->broken_odd_h_timings && > + ((mode->hdisplay % 2) || (mode->hsync_start % 2) || > + (mode->hsync_end % 2) || (mode->htotal % 2))) > + return MODE_H_ILLEGAL; > + > if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) > return MODE_CLOCK_HIGH; > > @@ -1950,6 +1960,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { > PHY_LANE_2, > PHY_LANE_CK, > }, > + .broken_odd_h_timings = true, > > .init_resources = vc5_hdmi_init_resources, > .csc_setup = vc5_hdmi_csc_setup, > @@ -1975,6 +1986,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { > PHY_LANE_CK, > PHY_LANE_2, > }, > + .broken_odd_h_timings = true, > > .init_resources = vc5_hdmi_init_resources, > .csc_setup = vc5_hdmi_csc_setup, > diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h > index af45b0d81dec..40e51ece8efe 100644 > --- a/drivers/gpu/drm/vc4/vc4_hdmi.h > +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h > @@ -62,6 +62,9 @@ struct vc4_hdmi_variant { > */ > enum vc4_hdmi_phy_channel phy_lane_mapping[4]; > > + /* The BCM2711 cannot deal with odd horizontal pixel timings */ > + bool broken_odd_h_timings; > + > /* Callback to get the resources (memory region, interrupts, > * clocks, etc) for that variant. > */ > -- > 2.26.2 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel