From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52C0BC47082 for ; Mon, 7 Jun 2021 10:10:36 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id B5705610C7 for ; Mon, 7 Jun 2021 10:10:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B5705610C7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 258A06B006C; Mon, 7 Jun 2021 06:10:35 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 208EF6B006E; Mon, 7 Jun 2021 06:10:35 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 0A9A06B0070; Mon, 7 Jun 2021 06:10:35 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0190.hostedemail.com [216.40.44.190]) by kanga.kvack.org (Postfix) with ESMTP id D041E6B006C for ; Mon, 7 Jun 2021 06:10:34 -0400 (EDT) Received: from smtpin27.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay04.hostedemail.com (Postfix) with ESMTP id 5F43F6C2D for ; Mon, 7 Jun 2021 10:10:34 +0000 (UTC) X-FDA: 78226508388.27.CC113BA Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) by imf29.hostedemail.com (Postfix) with ESMTP id 6596C544 for ; Mon, 7 Jun 2021 10:10:30 +0000 (UTC) Received: by mail-pf1-f171.google.com with SMTP id h12so9874612pfe.2 for ; Mon, 07 Jun 2021 03:10:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=ZHzx0rL9MdAUadCCLA+prC/o2aIaqUC2dlN2cCjZK0k=; b=GyQxI81dpz627gL97yPLABKwMlomoMsx6E+8IPCqZ6gIe4l9PEojvjhArY5suseGr2 33fSExAOzvtfeGoyCixLMGsBCNCgt35fQi4ys4Nk/fhEU+QjL33s9bNmGM8J9p5uuKXY RR+Uz4U3K6Wy93phgNtHRMxhbPjRaqRfnW1i1BFk3WmFynPosUf/xFH7dzbc0EtnS4+Z Z+3ero8E8S7BwH6az7lew9Cg4/hjymqGxFb957kn6WSjW+QvJKFTLadqZeTReuyl6MnZ 2tN6+WWL4QbZzEpUZ/TBN8sHjDAeAIj8vlOyY0NaqjiXlDmgEruLigcrAOF9krUqxMIf 0hVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=ZHzx0rL9MdAUadCCLA+prC/o2aIaqUC2dlN2cCjZK0k=; b=f40AhktFVu/XesDHYzPR7cseHyAjJnYj47+OucW6S/4ABT36l6IJtsAgUDanXyPS8c gF88MYnJntQ3jxQoZPxrbNLrTPyNHHviY3jiQejQ1uXZ0g0wtV8L68k1wXDCZ1WgsEvQ MrxbnV6mJ+E6JRZc6nkPE66NvAscOOPpdcESREo7lmriOEMULPVmrashY0TtIHQcpZEa keN0SXxlLUjgHSlhPWelUPRWYhtqb68tuIBATgYml4I73Ukg2x7L8XqihB/sNe3JN4vq HOWRnKn3NGpPxZFuJO4HTQcgKRGUd8UIpBoORk/lTUqXDyNMxbmRSf+LdUBgB71krcFR 1EJA== X-Gm-Message-State: AOAM531kId66TfSHN40expkajtbB7mfj8Tb8tknCD4EvtYqQNNskzzPa 7erucZaE/LibpL+uzeN3wmYJMJzKRfAtfj6NeeE= X-Google-Smtp-Source: ABdhPJxU3/30U9ZjhaW3RrNdBqW01I9VN2uCYqVO6cYMMCTHtI1kwgJ8wo69LzT+7mwiTGdIRqhJ1GQUYIkeRFANpcA= X-Received: by 2002:a63:7702:: with SMTP id s2mr17155353pgc.106.1623060633019; Mon, 07 Jun 2021 03:10:33 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a05:6a10:67d0:0:0:0:0 with HTTP; Mon, 7 Jun 2021 03:10:32 -0700 (PDT) In-Reply-To: <20210607055131.156184-1-aneesh.kumar@linux.ibm.com> References: <20210607055131.156184-1-aneesh.kumar@linux.ibm.com> From: Nick Piggin Date: Mon, 7 Jun 2021 20:10:32 +1000 Message-ID: Subject: Re: [PATCH v7 00/11] Speedup mremap on ppc64 To: "Aneesh Kumar K.V" Cc: "linux-mm@kvack.org" , "akpm@linux-foundation.org" , "mpe@ellerman.id.au" , "linuxppc-dev@lists.ozlabs.org" , "kaleshsingh@google.com" , "joel@joelfernandes.org" , Christophe Leroy , Linus Torvalds , "Kirill A . Shutemov" Content-Type: multipart/alternative; boundary="0000000000007ae6bc05c42a40ce" X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 6596C544 X-Stat-Signature: gz69pd9eax78oph9bfc3jzzjtjrg8md8 Authentication-Results: imf29.hostedemail.com; dkim=pass header.d=gmail.com header.s=20161025 header.b=GyQxI81d; dmarc=pass (policy=none) header.from=gmail.com; spf=pass (imf29.hostedemail.com: domain of npiggin@gmail.com designates 209.85.210.171 as permitted sender) smtp.mailfrom=npiggin@gmail.com X-HE-Tag: 1623060630-246000 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: --0000000000007ae6bc05c42a40ce Content-Type: text/plain; charset="UTF-8" On Monday, 7 June 2021, Aneesh Kumar K.V wrote: > > This patchset enables MOVE_PMD/MOVE_PUD support on power. This requires > the platform to support updating higher-level page tables without > updating page table entries. This also needs to invalidate the Page Walk > Cache on architecture supporting the same. > > Changes from v6: > * Update ppc64 flush_tlb_range to invalidate page walk cache. I'd really rather not do this, I'm not sure if micro bench mark captures everything. Page tables coming from L2/L3 probably aren't the primary purpose or biggest benefit of intermediate level caches. The situation on POWER with nest mmu (coherent accelerators) is magnified. They have huge page walk cashes to make up for the fact they don't have data caches for walking page tables which makes the invalidation more painful in terms of subsequent misses, but also latency to invalidate (can be order of microseconds whereas a page invalidate is a couple of orders of magnitude faster). Yes it is a deficiency of the ppc invalidation architecture, we are aware and would like to improve it but for now those is what we have. Thanks, Nick > * Add patches to fix race between mremap and page out > * Add patch to fix build error with page table levels 2 > > Changes from v5: > * Drop patch mm/mremap: Move TLB flush outside page table lock > * Add fixes for race between optimized mremap and page out > > Changes from v4: > * Change function name and arguments based on review feedback. > > Changes from v3: > * Fix build error reported by kernel test robot > * Address review feedback. > > Changes from v2: > * switch from using mmu_gather to flush_pte_tlb_pwc_range() > > Changes from v1: > * Rebase to recent upstream > * Fix build issues with tlb_gather_mmu changes > > > Aneesh Kumar K.V (11): > mm/mremap: Fix race between MOVE_PMD mremap and pageout > mm/mremap: Fix race between MOVE_PUD mremap and pageout > selftest/mremap_test: Update the test to handle pagesize other than 4K > selftest/mremap_test: Avoid crash with static build > mm/mremap: Convert huge PUD move to separate helper > mm/mremap: Don't enable optimized PUD move if page table levels is 2 > mm/mremap: Use pmd/pud_poplulate to update page table entries > powerpc/mm/book3s64: Fix possible build error > mm/mremap: Allow arch runtime override > powerpc/book3s64/mm: Update flush_tlb_range to flush page walk cache > powerpc/mm: Enable HAVE_MOVE_PMD support > > .../include/asm/book3s/64/tlbflush-radix.h | 2 + > arch/powerpc/include/asm/tlb.h | 6 + > arch/powerpc/mm/book3s64/radix_hugetlbpage.c | 8 +- > arch/powerpc/mm/book3s64/radix_tlb.c | 70 +++++++---- > arch/powerpc/platforms/Kconfig.cputype | 2 + > include/linux/rmap.h | 13 +- > mm/mremap.c | 104 +++++++++++++-- > mm/page_vma_mapped.c | 43 ++++--- > tools/testing/selftests/vm/mremap_test.c | 118 ++++++++++-------- > 9 files changed, 251 insertions(+), 115 deletions(-) > > -- > 2.31.1 > > --0000000000007ae6bc05c42a40ce Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Monday, 7 June 2021, Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> wrote:

This patchset enables MOVE_PMD/MOVE_PUD support on power. This requires
the platform to support updating higher-level page tables without
updating page table entries. This also needs to invalidate the Page Walk Cache on architecture supporting the same.

Changes from v6:
* Update ppc64 flush_tlb_range to invalidate page walk cache.<= div>
I'd really rather not do this, I'm not sure if m= icro bench mark captures everything.

Page tables c= oming from L2/L3 probably aren't the primary purpose or biggest benefit= of intermediate level caches.

The situation on PO= WER with nest mmu (coherent accelerators) is magnified. They have huge page= walk cashes to make up for the fact they don't have data caches for wa= lking page tables which makes the invalidation more painful in terms of sub= sequent misses, but also latency to invalidate (can be order of microsecond= s whereas a page invalidate is a couple of orders of magnitude faster).

Yes it is a deficiency of the ppc invalidation archit= ecture, we are aware and would like to improve it but for now those is what= we have.

Thanks,
Nick
=C2=A0<= /div>
* Add patches to fix race between mremap and page out
* Add patch to fix build error with page table levels 2

Changes from v5:
* Drop patch mm/mremap: Move TLB flush outside page table lock
* Add fixes for race between optimized mremap and page out

Changes from v4:
* Change function name and arguments based on review feedback.

Changes from v3:
* Fix build error reported by kernel test robot
* Address review feedback.

Changes from v2:
* switch from using mmu_gather to flush_pte_tlb_pwc_range()

Changes from v1:
* Rebase to recent upstream
* Fix build issues with tlb_gather_mmu changes


Aneesh Kumar K.V (11):
=C2=A0 mm/mremap: Fix race between MOVE_PMD mremap and pageout
=C2=A0 mm/mremap: Fix race between MOVE_PUD mremap and pageout
=C2=A0 selftest/mremap_test: Update the test to handle pagesize other than = 4K
=C2=A0 selftest/mremap_test: Avoid crash with static build
=C2=A0 mm/mremap: Convert huge PUD move to separate helper
=C2=A0 mm/mremap: Don't enable optimized PUD move if page table levels = is 2
=C2=A0 mm/mremap: Use pmd/pud_poplulate to update page table entries
=C2=A0 powerpc/mm/book3s64: Fix possible build error
=C2=A0 mm/mremap: Allow arch runtime override
=C2=A0 powerpc/book3s64/mm: Update flush_tlb_range to flush page walk cache=
=C2=A0 powerpc/mm: Enable HAVE_MOVE_PMD support

=C2=A0.../include/asm/book3s/64/tlbflush-radix.h=C2=A0 =C2=A0 |=C2=A0 = =C2=A02 +
=C2=A0arch/powerpc/include/asm/tlb.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A06 +
=C2=A0arch/powerpc/mm/book3s64/radix_hugetlbpage.c=C2=A0 |=C2=A0 =C2= =A08 +-
=C2=A0arch/powerpc/mm/book3s64/radix_tlb.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 |=C2=A0 70 +++++++----
=C2=A0arch/powerpc/platforms/Kconfig.cputype=C2=A0 =C2=A0 =C2=A0 =C2= =A0 |=C2=A0 =C2=A02 +
=C2=A0include/linux/rmap.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 13 +-
=C2=A0mm/mremap.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 104 = +++++++++++++--
=C2=A0mm/page_vma_mapped.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 43 ++++---
=C2=A0tools/testing/selftests/vm/mremap_test.c=C2=A0 =C2=A0 =C2=A0 | 1= 18 ++++++++++--------
=C2=A09 files changed, 251 insertions(+), 115 deletions(-)

--
2.31.1

--0000000000007ae6bc05c42a40ce-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EED20C47082 for ; Mon, 7 Jun 2021 22:46:04 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 258E8610A1 for ; Mon, 7 Jun 2021 22:46:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 258E8610A1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4FzT4B6cx2z3bs1 for ; Tue, 8 Jun 2021 08:46:02 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=GyQxI81d; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::532; helo=mail-pg1-x532.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=GyQxI81d; dkim-atps=neutral Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4Fz8Jc0CYKz2xxq for ; Mon, 7 Jun 2021 20:10:38 +1000 (AEST) Received: by mail-pg1-x532.google.com with SMTP id t9so13441630pgn.4 for ; Mon, 07 Jun 2021 03:10:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=ZHzx0rL9MdAUadCCLA+prC/o2aIaqUC2dlN2cCjZK0k=; b=GyQxI81dpz627gL97yPLABKwMlomoMsx6E+8IPCqZ6gIe4l9PEojvjhArY5suseGr2 33fSExAOzvtfeGoyCixLMGsBCNCgt35fQi4ys4Nk/fhEU+QjL33s9bNmGM8J9p5uuKXY RR+Uz4U3K6Wy93phgNtHRMxhbPjRaqRfnW1i1BFk3WmFynPosUf/xFH7dzbc0EtnS4+Z Z+3ero8E8S7BwH6az7lew9Cg4/hjymqGxFb957kn6WSjW+QvJKFTLadqZeTReuyl6MnZ 2tN6+WWL4QbZzEpUZ/TBN8sHjDAeAIj8vlOyY0NaqjiXlDmgEruLigcrAOF9krUqxMIf 0hVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=ZHzx0rL9MdAUadCCLA+prC/o2aIaqUC2dlN2cCjZK0k=; b=fWY1EGSWQ2iOzKtblMessP2NGUvNCHne/ZSZxbiYdqGUdwT7RDBvWfqwNBKtZ1fDtr g2n4FXLYHVloqWrU6J9KP82N4BR2s2Wardb12bQpkbEHgb5zFuatkx6SkOqsoFI8g9kD +LjsmLB4pFGObXk9tW6PoT0Kl92q6GlXZQKSSNjp+Xv+xkCgpzMrXIlQLGBJETMRMaEx aXyd9bAiMzyODGrP9V/Pyrsm24X+LTiB7OJfN3roqfLITDQvDIvuSBAgNRmW+fETNCWx EfweW2Vuxx3CLiJ0+z4rnYKWh/0k3mwo/J9f9jgU9UNpjuJ/VPxYJ+8ib60PcCrYHWeB rGGQ== X-Gm-Message-State: AOAM532auHwRLBECqsYi5QWHqjgWxq0lpK8b8KY8xOKQVyqbdJa8H2gk 1XXOelAyt6nrKul2MdYL3s2DtuW5mqzOZ9dYH14= X-Google-Smtp-Source: ABdhPJxU3/30U9ZjhaW3RrNdBqW01I9VN2uCYqVO6cYMMCTHtI1kwgJ8wo69LzT+7mwiTGdIRqhJ1GQUYIkeRFANpcA= X-Received: by 2002:a63:7702:: with SMTP id s2mr17155353pgc.106.1623060633019; Mon, 07 Jun 2021 03:10:33 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a05:6a10:67d0:0:0:0:0 with HTTP; Mon, 7 Jun 2021 03:10:32 -0700 (PDT) In-Reply-To: <20210607055131.156184-1-aneesh.kumar@linux.ibm.com> References: <20210607055131.156184-1-aneesh.kumar@linux.ibm.com> From: Nick Piggin Date: Mon, 7 Jun 2021 20:10:32 +1000 Message-ID: Subject: Re: [PATCH v7 00/11] Speedup mremap on ppc64 To: "Aneesh Kumar K.V" Content-Type: multipart/alternative; boundary="0000000000007ae6bc05c42a40ce" X-Mailman-Approved-At: Tue, 08 Jun 2021 08:45:37 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linus Torvalds , "linux-mm@kvack.org" , "kaleshsingh@google.com" , "joel@joelfernandes.org" , "Kirill A . Shutemov" , "akpm@linux-foundation.org" , "linuxppc-dev@lists.ozlabs.org" Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" --0000000000007ae6bc05c42a40ce Content-Type: text/plain; charset="UTF-8" On Monday, 7 June 2021, Aneesh Kumar K.V wrote: > > This patchset enables MOVE_PMD/MOVE_PUD support on power. This requires > the platform to support updating higher-level page tables without > updating page table entries. This also needs to invalidate the Page Walk > Cache on architecture supporting the same. > > Changes from v6: > * Update ppc64 flush_tlb_range to invalidate page walk cache. I'd really rather not do this, I'm not sure if micro bench mark captures everything. Page tables coming from L2/L3 probably aren't the primary purpose or biggest benefit of intermediate level caches. The situation on POWER with nest mmu (coherent accelerators) is magnified. They have huge page walk cashes to make up for the fact they don't have data caches for walking page tables which makes the invalidation more painful in terms of subsequent misses, but also latency to invalidate (can be order of microseconds whereas a page invalidate is a couple of orders of magnitude faster). Yes it is a deficiency of the ppc invalidation architecture, we are aware and would like to improve it but for now those is what we have. Thanks, Nick > * Add patches to fix race between mremap and page out > * Add patch to fix build error with page table levels 2 > > Changes from v5: > * Drop patch mm/mremap: Move TLB flush outside page table lock > * Add fixes for race between optimized mremap and page out > > Changes from v4: > * Change function name and arguments based on review feedback. > > Changes from v3: > * Fix build error reported by kernel test robot > * Address review feedback. > > Changes from v2: > * switch from using mmu_gather to flush_pte_tlb_pwc_range() > > Changes from v1: > * Rebase to recent upstream > * Fix build issues with tlb_gather_mmu changes > > > Aneesh Kumar K.V (11): > mm/mremap: Fix race between MOVE_PMD mremap and pageout > mm/mremap: Fix race between MOVE_PUD mremap and pageout > selftest/mremap_test: Update the test to handle pagesize other than 4K > selftest/mremap_test: Avoid crash with static build > mm/mremap: Convert huge PUD move to separate helper > mm/mremap: Don't enable optimized PUD move if page table levels is 2 > mm/mremap: Use pmd/pud_poplulate to update page table entries > powerpc/mm/book3s64: Fix possible build error > mm/mremap: Allow arch runtime override > powerpc/book3s64/mm: Update flush_tlb_range to flush page walk cache > powerpc/mm: Enable HAVE_MOVE_PMD support > > .../include/asm/book3s/64/tlbflush-radix.h | 2 + > arch/powerpc/include/asm/tlb.h | 6 + > arch/powerpc/mm/book3s64/radix_hugetlbpage.c | 8 +- > arch/powerpc/mm/book3s64/radix_tlb.c | 70 +++++++---- > arch/powerpc/platforms/Kconfig.cputype | 2 + > include/linux/rmap.h | 13 +- > mm/mremap.c | 104 +++++++++++++-- > mm/page_vma_mapped.c | 43 ++++--- > tools/testing/selftests/vm/mremap_test.c | 118 ++++++++++-------- > 9 files changed, 251 insertions(+), 115 deletions(-) > > -- > 2.31.1 > > --0000000000007ae6bc05c42a40ce Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Monday, 7 June 2021, Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> wrote:

This patchset enables MOVE_PMD/MOVE_PUD support on power. This requires
the platform to support updating higher-level page tables without
updating page table entries. This also needs to invalidate the Page Walk Cache on architecture supporting the same.

Changes from v6:
* Update ppc64 flush_tlb_range to invalidate page walk cache.<= div>
I'd really rather not do this, I'm not sure if m= icro bench mark captures everything.

Page tables c= oming from L2/L3 probably aren't the primary purpose or biggest benefit= of intermediate level caches.

The situation on PO= WER with nest mmu (coherent accelerators) is magnified. They have huge page= walk cashes to make up for the fact they don't have data caches for wa= lking page tables which makes the invalidation more painful in terms of sub= sequent misses, but also latency to invalidate (can be order of microsecond= s whereas a page invalidate is a couple of orders of magnitude faster).

Yes it is a deficiency of the ppc invalidation archit= ecture, we are aware and would like to improve it but for now those is what= we have.

Thanks,
Nick
=C2=A0<= /div>
* Add patches to fix race between mremap and page out
* Add patch to fix build error with page table levels 2

Changes from v5:
* Drop patch mm/mremap: Move TLB flush outside page table lock
* Add fixes for race between optimized mremap and page out

Changes from v4:
* Change function name and arguments based on review feedback.

Changes from v3:
* Fix build error reported by kernel test robot
* Address review feedback.

Changes from v2:
* switch from using mmu_gather to flush_pte_tlb_pwc_range()

Changes from v1:
* Rebase to recent upstream
* Fix build issues with tlb_gather_mmu changes


Aneesh Kumar K.V (11):
=C2=A0 mm/mremap: Fix race between MOVE_PMD mremap and pageout
=C2=A0 mm/mremap: Fix race between MOVE_PUD mremap and pageout
=C2=A0 selftest/mremap_test: Update the test to handle pagesize other than = 4K
=C2=A0 selftest/mremap_test: Avoid crash with static build
=C2=A0 mm/mremap: Convert huge PUD move to separate helper
=C2=A0 mm/mremap: Don't enable optimized PUD move if page table levels = is 2
=C2=A0 mm/mremap: Use pmd/pud_poplulate to update page table entries
=C2=A0 powerpc/mm/book3s64: Fix possible build error
=C2=A0 mm/mremap: Allow arch runtime override
=C2=A0 powerpc/book3s64/mm: Update flush_tlb_range to flush page walk cache=
=C2=A0 powerpc/mm: Enable HAVE_MOVE_PMD support

=C2=A0.../include/asm/book3s/64/tlbflush-radix.h=C2=A0 =C2=A0 |=C2=A0 = =C2=A02 +
=C2=A0arch/powerpc/include/asm/tlb.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A06 +
=C2=A0arch/powerpc/mm/book3s64/radix_hugetlbpage.c=C2=A0 |=C2=A0 =C2= =A08 +-
=C2=A0arch/powerpc/mm/book3s64/radix_tlb.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 |=C2=A0 70 +++++++----
=C2=A0arch/powerpc/platforms/Kconfig.cputype=C2=A0 =C2=A0 =C2=A0 =C2= =A0 |=C2=A0 =C2=A02 +
=C2=A0include/linux/rmap.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 13 +-
=C2=A0mm/mremap.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 104 = +++++++++++++--
=C2=A0mm/page_vma_mapped.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 43 ++++---
=C2=A0tools/testing/selftests/vm/mremap_test.c=C2=A0 =C2=A0 =C2=A0 | 1= 18 ++++++++++--------
=C2=A09 files changed, 251 insertions(+), 115 deletions(-)

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2.31.1

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