From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi0-x233.google.com (mail-oi0-x233.google.com [IPv6:2607:f8b0:4003:c06::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A529D1A1E6F for ; Tue, 6 Sep 2016 10:32:17 -0700 (PDT) Received: by mail-oi0-x233.google.com with SMTP id y2so83853890oie.0 for ; Tue, 06 Sep 2016 10:32:17 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <147318056046.30325.5100892122988191500.stgit@dwillia2-desk3.amr.corp.intel.com> <147318058165.30325.16762406881120129093.stgit@dwillia2-desk3.amr.corp.intel.com> From: Dan Williams Date: Tue, 6 Sep 2016 10:32:16 -0700 Message-ID: Subject: Re: [PATCH 4/5] mm: fix cache mode of dax pmd mappings List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: linux-nvdimm-bounces@lists.01.org Sender: "Linux-nvdimm" To: Matthew Wilcox Cc: "linux-nvdimm@lists.01.org" , Nilesh Choudhury , "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" , "linux-mm@kvack.org" , "akpm@linux-foundation.org" , "Kirill A. Shutemov" , Kai Zhang List-ID: On Tue, Sep 6, 2016 at 10:20 AM, Matthew Wilcox wrote: > I have no objection to this patch going in for now. > > Longer term, surely we want to track what mode the PFNs are mapped in? There are various bizarre suppositions out there about how persistent memory should be mapped, and it's probably better if the kernel ignores what the user specifies and keeps everything sane. I've read the dire warnings in the Intel architecture manual and I have no desire to deal with the inevitable bug reports on some hardware I don't own and requires twenty weeks of operation in order to observe the bug. Is there a way for userspace to establish mappings with different cache modes, besides via /dev/mem? That was the motivation for CONFIG_IO_STRICT_DEVMEM. _______________________________________________ Linux-nvdimm mailing list Linux-nvdimm@lists.01.org https://lists.01.org/mailman/listinfo/linux-nvdimm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936612AbcIFRcU (ORCPT ); Tue, 6 Sep 2016 13:32:20 -0400 Received: from mail-oi0-f44.google.com ([209.85.218.44]:36838 "EHLO mail-oi0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933688AbcIFRcR (ORCPT ); Tue, 6 Sep 2016 13:32:17 -0400 MIME-Version: 1.0 In-Reply-To: References: <147318056046.30325.5100892122988191500.stgit@dwillia2-desk3.amr.corp.intel.com> <147318058165.30325.16762406881120129093.stgit@dwillia2-desk3.amr.corp.intel.com> From: Dan Williams Date: Tue, 6 Sep 2016 10:32:16 -0700 Message-ID: Subject: Re: [PATCH 4/5] mm: fix cache mode of dax pmd mappings To: Matthew Wilcox Cc: "linux-nvdimm@lists.01.org" , Toshi Kani , Nilesh Choudhury , "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" , "linux-mm@kvack.org" , "akpm@linux-foundation.org" , Ross Zwisler , "Kirill A. Shutemov" , Kai Zhang Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id u86HWNLN010761 On Tue, Sep 6, 2016 at 10:20 AM, Matthew Wilcox wrote: > I have no objection to this patch going in for now. > > Longer term, surely we want to track what mode the PFNs are mapped in? There are various bizarre suppositions out there about how persistent memory should be mapped, and it's probably better if the kernel ignores what the user specifies and keeps everything sane. I've read the dire warnings in the Intel architecture manual and I have no desire to deal with the inevitable bug reports on some hardware I don't own and requires twenty weeks of operation in order to observe the bug. Is there a way for userspace to establish mappings with different cache modes, besides via /dev/mem? That was the motivation for CONFIG_IO_STRICT_DEVMEM. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 In-Reply-To: References: <147318056046.30325.5100892122988191500.stgit@dwillia2-desk3.amr.corp.intel.com> <147318058165.30325.16762406881120129093.stgit@dwillia2-desk3.amr.corp.intel.com> From: Dan Williams Date: Tue, 6 Sep 2016 10:32:16 -0700 Message-ID: Subject: Re: [PATCH 4/5] mm: fix cache mode of dax pmd mappings To: Matthew Wilcox Cc: "linux-nvdimm@lists.01.org" , Toshi Kani , Nilesh Choudhury , "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" , "linux-mm@kvack.org" , "akpm@linux-foundation.org" , Ross Zwisler , "Kirill A. Shutemov" , Kai Zhang Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Sender: owner-linux-mm@kvack.org List-ID: On Tue, Sep 6, 2016 at 10:20 AM, Matthew Wilcox wr= ote: > I have no objection to this patch going in for now. > > Longer term, surely we want to track what mode the PFNs are mapped in? T= here are various bizarre suppositions out there about how persistent memory= should be mapped, and it's probably better if the kernel ignores what the = user specifies and keeps everything sane. I've read the dire warnings in t= he Intel architecture manual and I have no desire to deal with the inevitab= le bug reports on some hardware I don't own and requires twenty weeks of op= eration in order to observe the bug. Is there a way for userspace to establish mappings with different cache modes, besides via /dev/mem? That was the motivation for CONFIG_IO_STRICT_DEVMEM. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org