From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi0-x241.google.com (mail-oi0-x241.google.com [IPv6:2607:f8b0:4003:c06::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 85DB022361E47 for ; Mon, 12 Feb 2018 14:59:22 -0800 (PST) Received: by mail-oi0-x241.google.com with SMTP id e15so12477759oiy.2 for ; Mon, 12 Feb 2018 15:05:12 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: <151847194459.58291.11339638808076622981.stgit@djiang5-desk3.ch.intel.com> From: Dan Williams Date: Mon, 12 Feb 2018 15:05:10 -0800 Message-ID: Subject: Re: [PATCH v2] libnvdimm: re-enable deep flush for pmem devices List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: linux-nvdimm-bounces@lists.01.org Sender: "Linux-nvdimm" To: Jeff Moyer Cc: "Zwisler, Ross" , Linux Kernel Mailing List , linux-nvdimm@lists.01.org List-ID: On Mon, Feb 12, 2018 at 2:53 PM, Jeff Moyer wrote: > Dave Jiang writes: > >> Re-enable deep flush so that users always have a way to be sure that a write >> does make it all the way out to the NVDIMM. The PMEM driver writes always >> make it "all the way to the NVDIMM", and it relies on the ADR mechanism to >> flush the write buffers on power failure. Deep flush is there to explicitly >> flush those write buffers to protect against (rare) ADR failure. >> This change prevents a regression in deep flush behavior so that applications >> can continue to depend on fsync() as a mechanism to trigger deep flush in the >> filesystem-dax case. > > That's still very confusing text. Specifically, the part where you say > that pmem driver writes always make it to the DIMM. I think the > changelog could start with "Deep flush is there to explicitly flush > write buffers...." Anyway, the fix looks right to me. I ended up changing the commit message to this, let me know if it reads better: libnvdimm: re-enable deep flush for pmem devices via fsync() Re-enable deep flush so that users always have a way to be sure that a write makes it all the way out to media. The PMEM driver writes always arrive at the NVDIMM, and it relies on the ADR (Asynchronous DRAM Refresh) mechanism to flush the write buffers on power failure. Deep flush is there to explicitly flush those write buffers to protect against (rare) ADR failure. This change prevents a regression in deep flush behavior so that applications can continue to depend on fsync() as a mechanism to trigger deep flush in the filesystem-DAX case. Fixes: 06e8ccdab15f4 ("acpi: nfit: Add support for detect platform CPU cache...") Signed-off-by: Dave Jiang Signed-off-by: Dan Williams _______________________________________________ Linux-nvdimm mailing list Linux-nvdimm@lists.01.org https://lists.01.org/mailman/listinfo/linux-nvdimm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932485AbeBLXFN (ORCPT ); Mon, 12 Feb 2018 18:05:13 -0500 Received: from mail-oi0-f67.google.com ([209.85.218.67]:38995 "EHLO mail-oi0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932336AbeBLXFL (ORCPT ); Mon, 12 Feb 2018 18:05:11 -0500 X-Google-Smtp-Source: AH8x227bwaFNXLIY2b16wo/HYYcWP8TSg+wwmiaLn6IJphITdNlZd69owoiZO6qE3b1goaSNKuiDXeNDoORHgaATqTo= MIME-Version: 1.0 In-Reply-To: References: <151847194459.58291.11339638808076622981.stgit@djiang5-desk3.ch.intel.com> From: Dan Williams Date: Mon, 12 Feb 2018 15:05:10 -0800 Message-ID: Subject: Re: [PATCH v2] libnvdimm: re-enable deep flush for pmem devices To: Jeff Moyer Cc: Dave Jiang , "Zwisler, Ross" , Linux Kernel Mailing List , linux-nvdimm@lists.01.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 12, 2018 at 2:53 PM, Jeff Moyer wrote: > Dave Jiang writes: > >> Re-enable deep flush so that users always have a way to be sure that a write >> does make it all the way out to the NVDIMM. The PMEM driver writes always >> make it "all the way to the NVDIMM", and it relies on the ADR mechanism to >> flush the write buffers on power failure. Deep flush is there to explicitly >> flush those write buffers to protect against (rare) ADR failure. >> This change prevents a regression in deep flush behavior so that applications >> can continue to depend on fsync() as a mechanism to trigger deep flush in the >> filesystem-dax case. > > That's still very confusing text. Specifically, the part where you say > that pmem driver writes always make it to the DIMM. I think the > changelog could start with "Deep flush is there to explicitly flush > write buffers...." Anyway, the fix looks right to me. I ended up changing the commit message to this, let me know if it reads better: libnvdimm: re-enable deep flush for pmem devices via fsync() Re-enable deep flush so that users always have a way to be sure that a write makes it all the way out to media. The PMEM driver writes always arrive at the NVDIMM, and it relies on the ADR (Asynchronous DRAM Refresh) mechanism to flush the write buffers on power failure. Deep flush is there to explicitly flush those write buffers to protect against (rare) ADR failure. This change prevents a regression in deep flush behavior so that applications can continue to depend on fsync() as a mechanism to trigger deep flush in the filesystem-DAX case. Fixes: 06e8ccdab15f4 ("acpi: nfit: Add support for detect platform CPU cache...") Signed-off-by: Dave Jiang Signed-off-by: Dan Williams