From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi0-x242.google.com (mail-oi0-x242.google.com [IPv6:2607:f8b0:4003:c06::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A53DE22361E46 for ; Mon, 12 Feb 2018 14:44:10 -0800 (PST) Received: by mail-oi0-x242.google.com with SMTP id 23so373595oip.12 for ; Mon, 12 Feb 2018 14:50:00 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <151847194459.58291.11339638808076622981.stgit@djiang5-desk3.ch.intel.com> References: <151847194459.58291.11339638808076622981.stgit@djiang5-desk3.ch.intel.com> From: Dan Williams Date: Mon, 12 Feb 2018 14:49:59 -0800 Message-ID: Subject: Re: [PATCH v2] libnvdimm: re-enable deep flush for pmem devices List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: linux-nvdimm-bounces@lists.01.org Sender: "Linux-nvdimm" To: Dave Jiang Cc: "Zwisler, Ross" , Linux Kernel Mailing List , linux-nvdimm@lists.01.org List-ID: On Mon, Feb 12, 2018 at 1:46 PM, Dave Jiang wrote: > Re-enable deep flush so that users always have a way to be sure that a write > does make it all the way out to the NVDIMM. The PMEM driver writes always > make it "all the way to the NVDIMM", and it relies on the ADR mechanism to > flush the write buffers on power failure. Deep flush is there to explicitly > flush those write buffers to protect against (rare) ADR failure. > This change prevents a regression in deep flush behavior so that applications > can continue to depend on fsync() as a mechanism to trigger deep flush in the > filesystem-dax case. > > Fixes: 06e8ccdab15f4 ("acpi: nfit: Add support for detect platform CPU cache flush on power loss") > > Signed-off-by: Dave Jiang Thanks Dave, applied. _______________________________________________ Linux-nvdimm mailing list Linux-nvdimm@lists.01.org https://lists.01.org/mailman/listinfo/linux-nvdimm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933269AbeBLWuC (ORCPT ); Mon, 12 Feb 2018 17:50:02 -0500 Received: from mail-oi0-f67.google.com ([209.85.218.67]:36894 "EHLO mail-oi0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932329AbeBLWuA (ORCPT ); Mon, 12 Feb 2018 17:50:00 -0500 X-Google-Smtp-Source: AH8x224QFIKZI2zW+XtViXn147VapwMnfcQ14pFpcV4F+klMYAqiVKX/4zJfPzl/+zZO8P+kmv6SlOPVNkOjj2CGpu4= MIME-Version: 1.0 In-Reply-To: <151847194459.58291.11339638808076622981.stgit@djiang5-desk3.ch.intel.com> References: <151847194459.58291.11339638808076622981.stgit@djiang5-desk3.ch.intel.com> From: Dan Williams Date: Mon, 12 Feb 2018 14:49:59 -0800 Message-ID: Subject: Re: [PATCH v2] libnvdimm: re-enable deep flush for pmem devices To: Dave Jiang Cc: "Zwisler, Ross" , Linux Kernel Mailing List , linux-nvdimm@lists.01.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 12, 2018 at 1:46 PM, Dave Jiang wrote: > Re-enable deep flush so that users always have a way to be sure that a write > does make it all the way out to the NVDIMM. The PMEM driver writes always > make it "all the way to the NVDIMM", and it relies on the ADR mechanism to > flush the write buffers on power failure. Deep flush is there to explicitly > flush those write buffers to protect against (rare) ADR failure. > This change prevents a regression in deep flush behavior so that applications > can continue to depend on fsync() as a mechanism to trigger deep flush in the > filesystem-dax case. > > Fixes: 06e8ccdab15f4 ("acpi: nfit: Add support for detect platform CPU cache flush on power loss") > > Signed-off-by: Dave Jiang Thanks Dave, applied.