From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D34AFC4727C for ; Wed, 30 Sep 2020 16:13:24 +0000 (UTC) Received: from ml01.01.org (ml01.01.org [198.145.21.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3FB1A206F7 for ; Wed, 30 Sep 2020 16:13:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=intel-com.20150623.gappssmtp.com header.i=@intel-com.20150623.gappssmtp.com header.b="PX1/Et52" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3FB1A206F7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-nvdimm-bounces@lists.01.org Received: from ml01.vlan13.01.org (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9209915198644; Wed, 30 Sep 2020 09:13:23 -0700 (PDT) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=2a00:1450:4864:20::642; helo=mail-ej1-x642.google.com; envelope-from=dan.j.williams@intel.com; receiver= Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 493511519863E for ; Wed, 30 Sep 2020 09:13:21 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id z23so3608595ejr.13 for ; Wed, 30 Sep 2020 09:13:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=B68i/03gO6ZR0stPp/XuIiWcgy0nxB559p48BCd6ARw=; b=PX1/Et52kin9Rxfq1UxAKtvLAZw8XEYjLfAunQK4XuD4V0feOzB3QEYw7v7ThbU3Mt mAiv2K0rHxn933lpLwwCB0wtsyk/Vkj9iawLQ63G7s/YSV5r1kqfzoqoJBOpyjemnwbR jPkFIZ+aCNen9BaOql/Q6UkMrcE1yeclcDXqo4pRtnReCRRV2KjdXlMJ2qcMYBn88j4a hn54Pujx2xVaIZJ/7UDT4TJHflGOZyAVNefQWpY1GlZxlpT9OsE4bf8lH2/2XnHpOhIz +oIvhB3mmC5yUm2M66+DuI52zIT9WH0bnVRAKm3+NziWfY9j9ACgASesmoLq29qnztc+ DZBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=B68i/03gO6ZR0stPp/XuIiWcgy0nxB559p48BCd6ARw=; b=l2AotiS4BuPknzE52NrpWaoOmuqPLz0AciJLn4bUB01g51GnZgDT4jYukIuoHj1NR9 zsSPvoP4YRH+4JQTD2RTZ5LHWnOMEpCxJoL+4q3USAh1qlPE0kO2rpKBLtEMkSoD4Xzd F2Iw92foJFdi0bfyLsqkzUewsMWydHa636o2QYXAYQtsedNGlNVQBvXZnyRp8Pcz3+8K XOhEoAOZFtWdEZau4CzSRxcxl6ikZcNwZr353ryRachHUwbO2MWL2s2ZI228F604IXqt YK6MYN0lcmr40a/jD/o8ep3igyStP+wAauvhlqo3EuM28Q28L+HleZ/FwNPz1bspMeS5 eYpA== X-Gm-Message-State: AOAM532AvV2q43KwXYz1I5giD0mJKLYqmtFJ34xJlOvkLvYm5SIaLGN7 1vB4Th/oAnpRC5uiwTzDnv/7opWqHko8jEWFmNbkKA== X-Google-Smtp-Source: ABdhPJxdHnKyHDYoMQeMMwxf000I8c4hJxQEZEzPq5LxM9cPBizoMqr58gmvU91MpkM9iwpTHzULwq9SHDscdiTmefI= X-Received: by 2002:a17:906:8143:: with SMTP id z3mr3481181ejw.323.1601482399413; Wed, 30 Sep 2020 09:13:19 -0700 (PDT) MIME-Version: 1.0 References: <160087928642.3520.17063139768910633998.stgit@dwillia2-desk3.amr.corp.intel.com> <160087929294.3520.12013578778066801369.stgit@dwillia2-desk3.amr.corp.intel.com> <20200929102512.GB21110@zn.tnic> In-Reply-To: <20200929102512.GB21110@zn.tnic> From: Dan Williams Date: Wed, 30 Sep 2020 09:13:07 -0700 Message-ID: Subject: Re: [PATCH v9 1/2] x86, powerpc: Rename memcpy_mcsafe() to copy_mc_to_{user, kernel}() To: Borislav Petkov Message-ID-Hash: 4XKYRJPZUNFLOSUX7DDY2JGZOSUENB7A X-Message-ID-Hash: 4XKYRJPZUNFLOSUX7DDY2JGZOSUENB7A X-MailFrom: dan.j.williams@intel.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; suspicious-header CC: Ingo Molnar , X86 ML , stable , "H. Peter Anvin" , Paul Mackerras , Thomas Gleixner , Peter Zijlstra , Mikulas Patocka , Alexander Viro , Arnaldo Carvalho de Melo , Linus Torvalds , Benjamin Herrenschmidt , Tony Luck , Michael Ellerman , linux-nvdimm , Linux Kernel Mailing List , Jan Kara X-Mailman-Version: 3.1.1 Precedence: list List-Id: "Linux-nvdimm developer list." Archived-At: List-Archive: List-Help: List-Post: List-Subscribe: List-Unsubscribe: Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Tue, Sep 29, 2020 at 3:25 AM Borislav Petkov wrote: > > On Wed, Sep 23, 2020 at 09:41:33AM -0700, Dan Williams wrote: > > The rename replaces a single top-level memcpy_mcsafe() with either > > copy_mc_to_user(), or copy_mc_to_kernel(). > > What is "copy_mc" supposed to mean? Especially if it is called that on > two arches... > > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > > index 7101ac64bb20..e876b3a087f9 100644 > > --- a/arch/x86/Kconfig > > +++ b/arch/x86/Kconfig > > @@ -75,7 +75,7 @@ config X86 > > select ARCH_HAS_PTE_DEVMAP if X86_64 > > select ARCH_HAS_PTE_SPECIAL > > select ARCH_HAS_UACCESS_FLUSHCACHE if X86_64 > > - select ARCH_HAS_UACCESS_MCSAFE if X86_64 && X86_MCE > > + select ARCH_HAS_COPY_MC if X86_64 > > X86_MCE is dropped here. So if I have a build which has > > # CONFIG_X86_MCE is not set > > One of those quirks like: > > /* > * CAPID0{7:6} indicate whether this is an advanced RAS SKU > * CAPID5{8:5} indicate that various NVDIMM usage modes are > * enabled, so memory machine check recovery is also enabled. > */ > if ((capid0 & 0xc0) == 0xc0 || (capid5 & 0x1e0)) > enable_copy_mc_fragile(); > > will still call enable_copy_mc_fragile() and none of those platforms > need MCE functionality? > > But there's a hunk in here which sets it in the MCE code: > > if (mca_cfg.recovery) > enable_copy_mc_fragile(); > > So which is it? They need it or they don't? > > The comment over copy_mc_to_kernel() says: > > * Call into the 'fragile' version on systems that have trouble > * actually do machine check recovery > > If CONFIG_X86_MCE is not set, I'll say. :) True, without CONFIG_X86_MCE there's no point in attempting the fragile copy because the #MC will go unhandled. At the same time the point of the new copy_mc_generic() is that it is suitable to use without CONFIG_X86_MCE as it's just a typical fast string copy instrumented for exception handling. So, I still think CONFIG_ARCH_HAS_COPY_MC is independent of CONFIG_X86_MCE, but enable_copy_mc_fragile() should be stubbed out by CONFIG_X86_MCE=n, will re-spin. > > > +++ b/arch/x86/lib/copy_mc.c > > @@ -0,0 +1,66 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* Copyright(c) 2016-2020 Intel Corporation. All rights reserved. */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +static DEFINE_STATIC_KEY_FALSE(copy_mc_fragile_key); > > + > > +void enable_copy_mc_fragile(void) > > +{ > > + static_branch_inc(©_mc_fragile_key); > > +} > > + > > +/** > > + * copy_mc_to_kernel - memory copy that that handles source exceptions > > One "that" is enough. Yup. _______________________________________________ Linux-nvdimm mailing list -- linux-nvdimm@lists.01.org To unsubscribe send an email to linux-nvdimm-leave@lists.01.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 950D5C4727E for ; Wed, 30 Sep 2020 16:13:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 37DF0206F7 for ; Wed, 30 Sep 2020 16:13:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=intel-com.20150623.gappssmtp.com header.i=@intel-com.20150623.gappssmtp.com header.b="PX1/Et52" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730104AbgI3QNV (ORCPT ); Wed, 30 Sep 2020 12:13:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725800AbgI3QNV (ORCPT ); Wed, 30 Sep 2020 12:13:21 -0400 Received: from mail-ej1-x644.google.com (mail-ej1-x644.google.com [IPv6:2a00:1450:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1D55C061755 for ; Wed, 30 Sep 2020 09:13:20 -0700 (PDT) Received: by mail-ej1-x644.google.com with SMTP id p15so3637892ejm.7 for ; Wed, 30 Sep 2020 09:13:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=B68i/03gO6ZR0stPp/XuIiWcgy0nxB559p48BCd6ARw=; b=PX1/Et52kin9Rxfq1UxAKtvLAZw8XEYjLfAunQK4XuD4V0feOzB3QEYw7v7ThbU3Mt mAiv2K0rHxn933lpLwwCB0wtsyk/Vkj9iawLQ63G7s/YSV5r1kqfzoqoJBOpyjemnwbR jPkFIZ+aCNen9BaOql/Q6UkMrcE1yeclcDXqo4pRtnReCRRV2KjdXlMJ2qcMYBn88j4a hn54Pujx2xVaIZJ/7UDT4TJHflGOZyAVNefQWpY1GlZxlpT9OsE4bf8lH2/2XnHpOhIz +oIvhB3mmC5yUm2M66+DuI52zIT9WH0bnVRAKm3+NziWfY9j9ACgASesmoLq29qnztc+ DZBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=B68i/03gO6ZR0stPp/XuIiWcgy0nxB559p48BCd6ARw=; b=BfKJSLGd7OKRjFMaN2ojV7k+I8bTzp/ecLerZldsN7weTyn/13yza0kmo/vgwlN3C7 uH5kIUmOHDa+t7xpQJhfbCFBIwL71iPAusQ1Al5zWaSV8O+0L+8SxA8quXtuAUaHdglX QkdROrybk6bXLDSngWji4zxc6bqSLYsW4/p26skaiD3b/qNdsyxLKPkID+0E3H31UHSz a+YT8qcpLwOLKUw/t3XSbeO79NxsPbWBXQ2xnMZ8FaA0Rrg0AbI0eSamguk4vZO/Ta9R rxqrir/RhKuRf6zbJQSV2nV8o8DMNsKoRCruselasWB3DfgKnV3ClUYDbsYnKvM5v4IK rvhA== X-Gm-Message-State: AOAM531fNEgU9AkrDVhiJtyORwrvqsicFVlG4kBk/tm2G5zJRdt6nBPP PW7j5okPuGYK6LA9BtGgsxbbobY/rfhyLLyJDN77oQ== X-Google-Smtp-Source: ABdhPJxdHnKyHDYoMQeMMwxf000I8c4hJxQEZEzPq5LxM9cPBizoMqr58gmvU91MpkM9iwpTHzULwq9SHDscdiTmefI= X-Received: by 2002:a17:906:8143:: with SMTP id z3mr3481181ejw.323.1601482399413; Wed, 30 Sep 2020 09:13:19 -0700 (PDT) MIME-Version: 1.0 References: <160087928642.3520.17063139768910633998.stgit@dwillia2-desk3.amr.corp.intel.com> <160087929294.3520.12013578778066801369.stgit@dwillia2-desk3.amr.corp.intel.com> <20200929102512.GB21110@zn.tnic> In-Reply-To: <20200929102512.GB21110@zn.tnic> From: Dan Williams Date: Wed, 30 Sep 2020 09:13:07 -0700 Message-ID: Subject: Re: [PATCH v9 1/2] x86, powerpc: Rename memcpy_mcsafe() to copy_mc_to_{user, kernel}() To: Borislav Petkov Cc: Ingo Molnar , X86 ML , stable , "H. Peter Anvin" , Paul Mackerras , Thomas Gleixner , Peter Zijlstra , Mikulas Patocka , Alexander Viro , Arnaldo Carvalho de Melo , Linus Torvalds , Benjamin Herrenschmidt , Tony Luck , Michael Ellerman , linux-nvdimm , Linux Kernel Mailing List , Jan Kara Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 29, 2020 at 3:25 AM Borislav Petkov wrote: > > On Wed, Sep 23, 2020 at 09:41:33AM -0700, Dan Williams wrote: > > The rename replaces a single top-level memcpy_mcsafe() with either > > copy_mc_to_user(), or copy_mc_to_kernel(). > > What is "copy_mc" supposed to mean? Especially if it is called that on > two arches... > > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > > index 7101ac64bb20..e876b3a087f9 100644 > > --- a/arch/x86/Kconfig > > +++ b/arch/x86/Kconfig > > @@ -75,7 +75,7 @@ config X86 > > select ARCH_HAS_PTE_DEVMAP if X86_64 > > select ARCH_HAS_PTE_SPECIAL > > select ARCH_HAS_UACCESS_FLUSHCACHE if X86_64 > > - select ARCH_HAS_UACCESS_MCSAFE if X86_64 && X86_MCE > > + select ARCH_HAS_COPY_MC if X86_64 > > X86_MCE is dropped here. So if I have a build which has > > # CONFIG_X86_MCE is not set > > One of those quirks like: > > /* > * CAPID0{7:6} indicate whether this is an advanced RAS SKU > * CAPID5{8:5} indicate that various NVDIMM usage modes are > * enabled, so memory machine check recovery is also enabled. > */ > if ((capid0 & 0xc0) == 0xc0 || (capid5 & 0x1e0)) > enable_copy_mc_fragile(); > > will still call enable_copy_mc_fragile() and none of those platforms > need MCE functionality? > > But there's a hunk in here which sets it in the MCE code: > > if (mca_cfg.recovery) > enable_copy_mc_fragile(); > > So which is it? They need it or they don't? > > The comment over copy_mc_to_kernel() says: > > * Call into the 'fragile' version on systems that have trouble > * actually do machine check recovery > > If CONFIG_X86_MCE is not set, I'll say. :) True, without CONFIG_X86_MCE there's no point in attempting the fragile copy because the #MC will go unhandled. At the same time the point of the new copy_mc_generic() is that it is suitable to use without CONFIG_X86_MCE as it's just a typical fast string copy instrumented for exception handling. So, I still think CONFIG_ARCH_HAS_COPY_MC is independent of CONFIG_X86_MCE, but enable_copy_mc_fragile() should be stubbed out by CONFIG_X86_MCE=n, will re-spin. > > > +++ b/arch/x86/lib/copy_mc.c > > @@ -0,0 +1,66 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* Copyright(c) 2016-2020 Intel Corporation. All rights reserved. */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +static DEFINE_STATIC_KEY_FALSE(copy_mc_fragile_key); > > + > > +void enable_copy_mc_fragile(void) > > +{ > > + static_branch_inc(©_mc_fragile_key); > > +} > > + > > +/** > > + * copy_mc_to_kernel - memory copy that that handles source exceptions > > One "that" is enough. Yup.