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From: Daniel Stone <daniel@fooishbar.org>
To: Nicolas Dufresne <nicolas@ndufresne.ca>
Cc: "Daniel Vetter" <daniel@ffwll.ch>,
	"Christian König" <christian.koenig@amd.com>,
	"Sharma, Shashank" <Shashank.Sharma@amd.com>,
	lkml <linux-kernel@vger.kernel.org>,
	dri-devel <dri-devel@lists.freedesktop.org>,
	linaro-mm-sig@lists.linaro.org,
	"Sumit Semwal" <sumit.semwal@linaro.org>,
	linux-media <linux-media@vger.kernel.org>
Subject: Re: DMA-buf and uncached system memory
Date: Thu, 23 Jun 2022 00:34:58 +0100	[thread overview]
Message-ID: <CAPj87rPYQNkgVEdHECQcHcYe2nCpgF3RYQKk_=wwhvJSxwHXCg@mail.gmail.com> (raw)
In-Reply-To: <9178e19f5c0e141772b61b759abaa0d176f902b6.camel@ndufresne.ca>

Hi Nicolas,

On Wed, 22 Jun 2022 at 20:39, Nicolas Dufresne <nicolas@ndufresne.ca> wrote:
> Le mardi 16 février 2021 à 10:25 +0100, Daniel Vetter a écrit :
> > So I think if AMD also guarantees to drop clean cachelines just do the
> > same thing we do right now for intel integrated + discrete amd, but in
> > reserve. It's fragile, but it does work.
>
> Sorry to disrupt, but if you pass V4L2 vmalloc data to Intel display driver, you
> also get nice dirt on the screen. If you have a UVC webcam that produces a pixel
> format compatible with your display, you can reproduce the issue quite easily
> with:
>
>   gst-launch-1.0 v4l2src device=/dev/video0 ! kmssink
>
> p.s. some frame-rate are less likely to exhibit the issue, make sure you create
> movement to see it.

Right, this is because the UVC data in a vmalloc() area is not
necessarily flushed from the CPU cache, and the importer expects it
will be.

> The only solution I could think of (not implemented) was to detect in the
> attach() call what the importers can do (with dev->coherent_dma_mask if I
> recall), and otherwise flush the cache immediately and start flushing the cache
> from now on signalling it for DQBUF (in vb2 workqueue or dqbuf ioctl, I don't
> have an idea yet). I bet this idea is inapplicable to were you have fences, we
> don't have that in v4l2.
>
> This idea was hinted by Robert Becket (now in CC), but perhaps I picked it up
> wrong, explaining it wrong, etc. I'm no expert, just noticed there wasn't really
> a good plan for that, so one needs to make one up. I'm not aware oh an importer
> could know how the memory was allocated by the exporter, and worst, how an
> importer could figure-out that the export is going to produce buffer with hot
> CPU cache (UVC driver does memcpy from USB chunks of variable size to produce a
> fixed size image).

This is exactly what Christian was saying above.

Cheers,
Daniel

WARNING: multiple messages have this Message-ID (diff)
From: Daniel Stone <daniel@fooishbar.org>
To: Nicolas Dufresne <nicolas@ndufresne.ca>
Cc: "Sharma, Shashank" <Shashank.Sharma@amd.com>,
	lkml <linux-kernel@vger.kernel.org>,
	dri-devel <dri-devel@lists.freedesktop.org>,
	"Sumit Semwal" <sumit.semwal@linaro.org>,
	linaro-mm-sig@lists.linaro.org,
	"Christian König" <christian.koenig@amd.com>,
	linux-media <linux-media@vger.kernel.org>
Subject: Re: DMA-buf and uncached system memory
Date: Thu, 23 Jun 2022 00:34:58 +0100	[thread overview]
Message-ID: <CAPj87rPYQNkgVEdHECQcHcYe2nCpgF3RYQKk_=wwhvJSxwHXCg@mail.gmail.com> (raw)
In-Reply-To: <9178e19f5c0e141772b61b759abaa0d176f902b6.camel@ndufresne.ca>

Hi Nicolas,

On Wed, 22 Jun 2022 at 20:39, Nicolas Dufresne <nicolas@ndufresne.ca> wrote:
> Le mardi 16 février 2021 à 10:25 +0100, Daniel Vetter a écrit :
> > So I think if AMD also guarantees to drop clean cachelines just do the
> > same thing we do right now for intel integrated + discrete amd, but in
> > reserve. It's fragile, but it does work.
>
> Sorry to disrupt, but if you pass V4L2 vmalloc data to Intel display driver, you
> also get nice dirt on the screen. If you have a UVC webcam that produces a pixel
> format compatible with your display, you can reproduce the issue quite easily
> with:
>
>   gst-launch-1.0 v4l2src device=/dev/video0 ! kmssink
>
> p.s. some frame-rate are less likely to exhibit the issue, make sure you create
> movement to see it.

Right, this is because the UVC data in a vmalloc() area is not
necessarily flushed from the CPU cache, and the importer expects it
will be.

> The only solution I could think of (not implemented) was to detect in the
> attach() call what the importers can do (with dev->coherent_dma_mask if I
> recall), and otherwise flush the cache immediately and start flushing the cache
> from now on signalling it for DQBUF (in vb2 workqueue or dqbuf ioctl, I don't
> have an idea yet). I bet this idea is inapplicable to were you have fences, we
> don't have that in v4l2.
>
> This idea was hinted by Robert Becket (now in CC), but perhaps I picked it up
> wrong, explaining it wrong, etc. I'm no expert, just noticed there wasn't really
> a good plan for that, so one needs to make one up. I'm not aware oh an importer
> could know how the memory was allocated by the exporter, and worst, how an
> importer could figure-out that the export is going to produce buffer with hot
> CPU cache (UVC driver does memcpy from USB chunks of variable size to produce a
> fixed size image).

This is exactly what Christian was saying above.

Cheers,
Daniel

  reply	other threads:[~2022-06-22 23:35 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-15  8:58 DMA-buf and uncached system memory Christian König
2021-02-15  8:58 ` Christian König
2021-02-15  9:06 ` Simon Ser
2021-02-15  9:06   ` Simon Ser
2021-02-15  9:34   ` Christian König
2021-02-15  9:34     ` Christian König
2021-02-15 11:53     ` Lucas Stach
2021-02-15 11:53       ` Lucas Stach
2021-02-15 12:04       ` Christian König
2021-02-15 12:04         ` Christian König
2021-02-15 12:16         ` Lucas Stach
2021-02-15 12:16           ` Lucas Stach
2021-02-15 12:25           ` Christian König
2021-02-15 12:25             ` Christian König
2021-02-15 14:41         ` David Laight
2021-02-15 14:41           ` David Laight
2021-02-15 14:54           ` [Linaro-mm-sig] " Christian König
2021-02-15 14:54             ` Christian König
2021-02-15  9:49 ` Thomas Zimmermann
2021-02-15  9:49   ` Thomas Zimmermann
2021-02-15 12:00   ` Thomas Zimmermann
2021-02-15 12:00     ` Thomas Zimmermann
2021-02-15 12:10     ` Christian König
2021-02-15 12:10       ` Christian König
2021-02-15 20:46       ` Nicolas Dufresne
2021-02-15 20:46         ` Nicolas Dufresne
2021-02-15 20:39 ` Nicolas Dufresne
2021-02-15 20:39   ` Nicolas Dufresne
2022-06-21 10:17   ` Andy.Hsieh
2022-06-21 10:34     ` Christian König
2022-06-21 15:42       ` Nicolas Dufresne
2022-06-21 15:42         ` Nicolas Dufresne
2022-06-22  9:05         ` [Linaro-mm-sig] " Christian König
2022-06-22  9:05           ` Christian König
2021-02-16  9:25 ` Daniel Vetter
2021-02-16  9:25   ` Daniel Vetter
2022-06-22 19:39   ` Nicolas Dufresne
2022-06-22 19:39     ` Nicolas Dufresne
2022-06-22 23:34     ` Daniel Stone [this message]
2022-06-22 23:34       ` Daniel Stone
2022-06-23  6:59       ` Christian König
2022-06-23  6:59         ` Christian König
2022-06-23  7:13         ` Pekka Paalanen
2022-06-23  7:13           ` Pekka Paalanen
2022-06-23  7:26           ` Christian König
2022-06-23  7:26             ` Christian König
2022-06-23  8:04             ` Lucas Stach
2022-06-23  8:14               ` Christian König
2022-06-23  8:58                 ` Lucas Stach
2022-06-23  9:09                   ` Christian König
2022-06-23  9:33                     ` Lucas Stach
2022-06-23  9:46                       ` Christian König
2022-06-23 10:13                         ` Lucas Stach
2022-06-23 11:10                           ` Christian König
2022-06-23 11:27                             ` Daniel Stone
2022-06-23 11:27                               ` Daniel Stone
2022-06-23 11:32                               ` Christian König
2022-06-23 11:32                                 ` Christian König
2022-06-24 22:02                                 ` [Linaro-mm-sig] " Daniel Vetter
2022-06-24 22:02                                   ` Daniel Vetter
2022-07-04 13:48                                   ` Christian König
2022-08-09 14:46                                     ` Daniel Vetter
2022-08-09 14:46                                       ` Daniel Vetter
2022-08-10  5:55                                       ` Christian König
2022-06-23 11:29                             ` Lucas Stach
2022-06-23 11:54                               ` Christian König
2022-06-23 12:14                                 ` Lucas Stach
2022-06-23 12:52                                   ` Christian König
2022-06-23 15:26                                     ` Lucas Stach
2022-06-24  6:54                                       ` Christian König
2022-06-24  8:10                                         ` Lucas Stach
2022-06-27 13:54                       ` Nicolas Dufresne
2022-06-27 14:06                         ` Lucas Stach
2022-06-27 14:30                           ` Nicolas Dufresne
2022-06-27 13:51                   ` Nicolas Dufresne
2022-06-23  8:13 ` Thomas Zimmermann
2022-06-23  8:26   ` Christian König
2022-06-23  8:42     ` Thomas Zimmermann
2022-08-09 15:01 ` Rob Clark
2022-08-09 15:01   ` Rob Clark

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