From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Glass Date: Sat, 11 May 2013 09:09:07 -0600 Subject: [U-Boot] [PATCH] EXYNOS: SPI: Minimise access to SPI FIFO level In-Reply-To: <1363961377-18835-1-git-send-email-rajeshwari.s@samsung.com> References: <1363961377-18835-1-git-send-email-rajeshwari.s@samsung.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Fri, Mar 22, 2013 at 8:09 AM, Rajeshwari Shinde wrote: > Accessing SPI registers is slow, but access to the FIFO level register > in particular seems to be extraordinarily expensive (I measure up to > 600ns). Perhaps it is required to synchronise with the SPI byte output > logic which might run at 1/8th of the 40MHz SPI speed (just a guess). > > Reduce access to this register by filling up and emptying FIFOs > more completely, rather than just one word each time around the inner > loop. > > Since the rxfifo value will now likely be much greater that what we read > before we fill the txfifo, we only fill the txfifo halfway. This is > because if the txfifo is empty, but the rxfifo has data in it, then writing > too much data to the txfifo may overflow the rxfifo as data arrives. > > This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow. > > Signed-off-by: Simon Glass > Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass