From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42DD3C433FE for ; Fri, 30 Sep 2022 23:49:50 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5A77C84DBD; Sat, 1 Oct 2022 01:49:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="LKsJCgl3"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 3628084DBD; Sat, 1 Oct 2022 01:49:20 +0200 (CEST) Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 52CE484C30 for ; Sat, 1 Oct 2022 01:49:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@google.com Received: by mail-wr1-x42e.google.com with SMTP id w18so266210wro.7 for ; Fri, 30 Sep 2022 16:49:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=4leNzQzQPobIvpidgrPgH4ygi4Q3MPHjXe+oSZqT+TU=; b=LKsJCgl3JcJQ56Ig59Mpl3ivekzbSxUNZN1eTdCC0E0CAbNxPMayQYAskfaWzOoFsd RhH7fSMjHTxez/Xvtmmx+fNnZY7+BCbw8yymx1EG4yjaVpNSozGGvVf0ysTdPhxmMWlb deM6s71dQy23FZtL6UAHA0gPQPf2pPcA0qlNI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=4leNzQzQPobIvpidgrPgH4ygi4Q3MPHjXe+oSZqT+TU=; b=rSyIn6qzAbG2GslJLcVa1u+jtE+D9kyqMBzzrYbinAYG+H/ONd2kAQMEzmhw8Y4ryv s3OW2oQlhd4cOp17s3Awf2YOI3NFoAfvcBYDS0ospVTRJKYYCY8IdMq9uJON2BLF1fUZ dNd7RwiSdn3rGYtIlEqkCfxCKhmkolxSQZ8dcvrWzlSpR5ptufpNPUj+O0dc5dIljz5s cbVmsKf8sU3BCEMvA4TffQNR1Me5dq23ab0MgIVuLdkPFN5DX6nkvRHosYWxMCZ0Z/NP 91nGaCC3UleHRHEj38zwUnMcMZGtYXthAv/hl7E+t68Cgk3EWCUemwSClCgMsQcVNSXD OboQ== X-Gm-Message-State: ACrzQf2hP+tAiT1xkpNyfinBA1OKtZtzO15sJ3WTioR91qCsryx2sZX1 tYeZvNXSma4PhCiKPCpXdJA3krf8AFpSRchVTI/rAw== X-Google-Smtp-Source: AMsMyM75/VVeFPpPv7fIAa7JBo6V/4KfdTsl8l6m62kIlFgKlrTYDKa34YeJ8DIz1PLHD4+2ITp+1POpE07JGdycA4w= X-Received: by 2002:a05:6000:18a1:b0:22a:f4c2:c9e6 with SMTP id b1-20020a05600018a100b0022af4c2c9e6mr7443934wri.71.1664581755618; Fri, 30 Sep 2022 16:49:15 -0700 (PDT) MIME-Version: 1.0 References: <20220929095639.355675-1-mchitale@ventanamicro.com> <20220929095639.355675-3-mchitale@ventanamicro.com> In-Reply-To: From: Simon Glass Date: Fri, 30 Sep 2022 17:49:03 -0600 Message-ID: Subject: Re: [RFC PATCH v1 2/3] nvme: pci: Enable for SPL To: Mayuresh Chitale Cc: Bin Meng , U-Boot Mailing List , Heinrich Schuchardt , Rick Chen , Leo Content-Type: text/plain; charset="UTF-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Hi Mayuresh, On Fri, 30 Sept 2022 at 10:58, Mayuresh Chitale wrote: > > Hi Simon, > > On Fri, Sep 30, 2022 at 5:26 AM Simon Glass wrote: >> >> Hi Mayuresh, >> >> On Thu, 29 Sept 2022 at 03:57, Mayuresh Chitale >> wrote: >> > >> > Build PCI NVMe driver when enabled for SPI and enable dm-pre-reloc for >> > the driver. Also enable PCI_PNP for SPL which is required to auto >> > configure the PCIe devices. >> > >> > Signed-off-by: Mayuresh Chitale >> > --- >> > drivers/Makefile | 2 +- >> > drivers/nvme/Makefile | 2 +- >> > drivers/nvme/nvme_pci.c | 1 + >> > drivers/pci/Kconfig | 7 +++++++ >> > drivers/pci/pci-uclass.c | 3 ++- >> > 5 files changed, 12 insertions(+), 3 deletions(-) >> > >> > diff --git a/drivers/Makefile b/drivers/Makefile >> > index eba9940231..581ae9f819 100644 >> > --- a/drivers/Makefile >> > +++ b/drivers/Makefile >> > @@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ >> > obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ >> > obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/ >> > obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ >> > +obj-$(CONFIG_$(SPL_)NVME) += nvme/ >> > obj-$(CONFIG_XEN) += xen/ >> > obj-$(CONFIG_$(SPL_)FPGA) += fpga/ >> > >> > @@ -86,7 +87,6 @@ obj-y += crypto/ >> > obj-$(CONFIG_FASTBOOT) += fastboot/ >> > obj-y += misc/ >> > obj-$(CONFIG_MMC) += mmc/ >> > -obj-$(CONFIG_NVME) += nvme/ >> > obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/ >> > obj-y += dfu/ >> > obj-$(CONFIG_PCH) += pch/ >> > diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile >> > index fa7b619446..fd3e68a91d 100644 >> > --- a/drivers/nvme/Makefile >> > +++ b/drivers/nvme/Makefile >> > @@ -4,4 +4,4 @@ >> > >> > obj-y += nvme-uclass.o nvme.o nvme_show.o >> > obj-$(CONFIG_NVME_APPLE) += nvme_apple.o >> > -obj-$(CONFIG_NVME_PCI) += nvme_pci.o >> > +obj-$(CONFIG_$(SPL_)NVME_PCI) += nvme_pci.o >> > diff --git a/drivers/nvme/nvme_pci.c b/drivers/nvme/nvme_pci.c >> > index 36bf9c5ffb..16d8b9fff7 100644 >> > --- a/drivers/nvme/nvme_pci.c >> > +++ b/drivers/nvme/nvme_pci.c >> > @@ -39,6 +39,7 @@ U_BOOT_DRIVER(nvme) = { >> > .bind = nvme_bind, >> > .probe = nvme_probe, >> > .priv_auto = sizeof(struct nvme_dev), >> > + .flags = DM_FLAG_PRE_RELOC, >> >> Why is this here? It is only applicable on some boards. >> >> Instead, add the appropriate tag (e.g. u-boot,dm-spl) to the device node. > > > I am not sure how that can be done for PCI devices as those would be probed at run time. Could you please point to any examples? Also, the pci_find_and_bind_driver function only checks for this flag in the drivers when binding the devices See host-bridge@0,0 in chromebook_coral.dts for an example of using the u-boot,dm-pre-reloc flag. Note that pci_find_and_bind_driver() is only called if the device tree lacks anything. Which board is this for? Regards, Simon