From mboxrd@z Thu Jan  1 00:00:00 1970
From: Simon Glass <sjg@chromium.org>
Date: Sat, 24 Apr 2021 16:56:16 +1200
Subject: [PATCH 03/17] x86: Allow coreboot serial driver to guess the UART
In-Reply-To: <CAEUhbmXYn53yAmCyy0S8Lg4GQsSmMVE=s_VrzUt42GSeducvKg@mail.gmail.com>
References: <20210407043228.2268429-1-sjg@chromium.org>
 <20210407163159.3.I967ea8c85e009f870c7aa944372d32c990f1b14a@changeid>
 <CAEUhbmXYn53yAmCyy0S8Lg4GQsSmMVE=s_VrzUt42GSeducvKg@mail.gmail.com>
Message-ID: <CAPnjgZ0XDsmadkD0m87aU3x_8A6P_LUieiy_0-Lc4iYweeN1Bg@mail.gmail.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

Hi Bin,

On Thu, 8 Apr 2021 at 14:23, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Wed, Apr 7, 2021 at 12:32 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > At present this driver relies on coreboot to provide information about
> > the console UART. However if coreboot is not compiled with the UART
> > enabled, the information is left out. This configuration is quite
> > common, e.g. with shipping x86-based Chrome OS Chromebooks.
> >
> > Add a way to determine the UART settings in this case, using a
> > hard-coded list of PCI IDs.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> >  drivers/serial/serial_coreboot.c | 68 ++++++++++++++++++++++++++++----
> >  include/pci_ids.h                |  1 +
> >  2 files changed, 61 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c
> > index de09c8681f5..4b4619432d8 100644
> > --- a/drivers/serial/serial_coreboot.c
> > +++ b/drivers/serial/serial_coreboot.c
> > @@ -11,19 +11,71 @@
> >  #include <serial.h>
> >  #include <asm/cb_sysinfo.h>
> >
> > +static const struct pci_device_id ids[] = {
> > +       { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL_UART2) },
> > +       {},
> > +};
> > +
> > +/*
> > + * Coreboot only sets up the UART if it uses it and doesn't bother to put the
> > + * details in sysinfo if it doesn't. Try to guess in that case, using devices
> > + * we know about
> > + *
> > + * @plat: Platform data to fill in
> > + * @return 0 if found, -ve if no UART was found
> > + */
> > +static int guess_uart(struct ns16550_plat *plat)
>
> This is really not a guess, but use a pre-configured platform data.
> Also this only work for Apollo Lake board, and will break other boards
> if they don't have cbinfo available.

Which bit of it breaks other boards?

>
> Why not just simply put a serial node in the device tree and we are all done?

See my other email...I am trying to make this boot on any board that
coreboot supports.

[..]

Regards,
Simon