From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Glass Date: Fri, 13 Jan 2012 09:55:25 -0800 Subject: [U-Boot] [PATCH 12/14] tegra: Set vdd_core and vdd_cpu to high In-Reply-To: <4F0C8620.2060003@nvidia.com> References: <1324927987-13100-1-git-send-email-sjg@chromium.org> <1324927987-13100-13-git-send-email-sjg@chromium.org> <4F0C8620.2060003@nvidia.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Stephen, On Tue, Jan 10, 2012 at 10:40 AM, Stephen Warren wrote: > On 12/26/2011 12:33 PM, Simon Glass wrote: >> From: Jimmy Zhang >> >> At cold boot, the default voltage supplied by pmu is not high enough >> to support emc to run at its highest clock frequency. The code added >> here is to update the default vdd_core and vdd_cpu to higher values. >> >> (Sorry if I have mangled this comment) > > ?? Remove that last line? Actually that is the truth! Unfortunately this commit originally brought in the whole PMU and assorted other things in one big patch. I split those things out in this series, and I think this may actually relate to something else. > > I thought this issue only affected the T25 SKU when coupled with a > particular voltage regulator that wasn't reprogrammed to explicitly > support T25. Hence, shouldn't this code only be enabled for specific boards? > >> diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c > ... >> ?/* >> + * Routine: power_det_init >> + * Description: turn off power detects >> + */ >> +static void power_det_init(void) >> +{ >> +#if defined(CONFIG_TEGRA2) >> + ? ? struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; >> + >> + ? ? /* turn off power detects */ >> + ? ? writel(0, &pmc->pmc_pwr_det_latch); >> + ? ? writel(0, &pmc->pmc_pwr_det); >> +#endif >> +} > > I can't tell how that code relates to the commit description. Neither could I, hence my comment. But I think I just made a mistake - I have been back through the commits and actually I think it should be: Tegra core power rail has leakage voltage around 0.2V while system in suspend mode. The source of the leakage should be coming from PMC power detect logic for IO rails power detection. That can be disabled by writing a '0' to PWR_DET_LATCH followed by writing '0' to PWR_DET (APBDEV_PMC_PWR_DET_0). so I will change it. Regards, Simon > > -- > nvpublic